System Level Simulation Wrapper for Hybrid IP Modeling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current system design simulations for semiconductor devices, such as ASICs and FPGAs, require all IP blocks to be modeled using cycle accurate HDL models, which is computationally expensive and not scalable, limiting the ability to incrementally substitute cycle accurate HDL models with system level models without significant changes to the system design.
Innovation Solution
A system level simulation wrapper that provides pin-accurate and bus-cycle accurate communication through a switch and optional translation layers, allowing either cycle accurate HDL models or system level models of IP blocks to be used for simulation, enabling incremental substitution of cycle accurate HDL models with system level models of varying granularity without requiring additional changes to the system design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cycle accurate HDL models are used for all IP blocks, then simulation accuracy is maintained, but computational expense increases and scalability decreases
Solution Approach 1:
The simulation system is segmented into different modeling layers (cycle-accurate HDL models and system-level models). The wrapper allows selective substitution of IP block models at the system-level without affecting the accuracy of the remaining cycle-accurate portions, thereby reducing overall computational expense while maintaining simulation accuracy for critical components.
Solution Approach 2:
A simulation wrapper acts as an intermediary layer between the bus interface and IP block models. This wrapper provides translation and adaptation mechanisms that enable system-level models to interface correctly with cycle-accurate bus interfaces, allowing accurate simulation without requiring all IP blocks to be cycle-accurate.
2Manufacturing precision
If cycle accurate HDL models are used for all IP blocks, then pin-accuracy and bus-cycle accuracy are maintained, but device complexity and scalability worsen
Solution Approach 1:
The modeling complexity is segmented and distributed selectively. Critical IP blocks requiring pin-accuracy and bus-cycle accuracy use cycle-accurate HDL models, while non-critical IP blocks use simpler system-level models. The wrapper manages the interface between these different complexity levels, maintaining overall simulation accuracy without requiring uniform high complexity across all components.
Solution Approach 2:
The simulation wrapper provides universal interface functionality that works with both cycle-accurate HDL models and system-level models. It implements translation layers and adaptation logic that enable different model types to interoperate through a common interface, allowing the system to accommodate multiple modeling approaches without increasing device complexity.
3Use of energy by moving object
If system level models are substituted for cycle accurate HDL models, then computational expense decreases, but the ability to maintain pin-accuracy and bus-cycle accuracy without significant changes to system design is challenged
Solution Approach 1:
The simulation wrapper serves as a mediator that translates between system-level model interfaces and cycle-accurate bus interfaces. It implements pin-accuracy and bus-cycle accuracy through translation layers that adapt system-level model outputs to match the required interface specifications, enabling model substitution without significant changes to the system design.
Solution Approach 2:
The wrapper creates a virtual representation of the IP block behavior at the system-level that copies the essential functional characteristics while maintaining pin-accuracy and bus-cycle accuracy through translation. This allows system-level models to substitute for cycle-accurate models while preserving the necessary interface behavior through copied and adapted signal characteristics.
Data Source
AI summary
A system level simulation wrapper includes a plurality of port interfaces configured to provide pin accurate and bus cycle accurate communication. The system also includes a switch coupled to the plurality of port interfaces. The switch is selectively configured to communicate with a Cycle Accurate hardware description language (HDL) model of an intellectual property (IP) block or a system level model of the IP block.