Time-Multiplexed Simulator Scheduling for Matrix-Vector Latency
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Solution Overview
Problem
Simulators face inefficiencies in resource utilization during calculation tasks, leading to imbalances between latency and required hardware resources, particularly in complex technical systems like power electronics circuits.
Innovation Solution
The simulator employs an arithmetic unit with multipliers and adders configured for time-division multiplexing, where a scheduler assigns output values from multipliers to adders, allowing for parallelization of computing tasks and improved resource utilization through staggered task execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional simulation methods are used, then hardware resources are fully allocated, but resource utilization efficiency is low and latency increases
Solution Approach 1:
The patent implements dynamic resource allocation by making the arithmetic unit configurable between different operational modes (full parallel execution vs. time-division multiplexing). The system can adaptively switch between these modes based on simulation requirements, allowing the same hardware to serve multiple purposes efficiently. This dynamic reconfiguration resolves the contradiction by enabling high resource utilization through TDM while maintaining acceptable latency through mode switching.
Solution Approach 2:
The patent applies time-division multiplexing where the single arithmetic unit alternates between executing different tasks in periodic time slots. The control unit schedules matrix-vector multiplications and other computational tasks in alternating periods, allowing the arithmetic unit to serve multiple functions sequentially. This periodic action achieves high resource utilization by eliminating idle hardware while managing latency through careful scheduling of task execution periods.
2Speed
If more hardware resources are allocated, then calculation speed increases, but hardware complexity and resource requirements increase
Solution Approach 1:
The patent makes the arithmetic unit universal by enabling it to perform multiple different computational tasks through configuration. The same arithmetic unit can execute matrix-vector multiplications, vector operations, and other computational tasks by receiving different configuration parameters. This multi-functionality eliminates the need for dedicated hardware for each task type, reducing hardware complexity while maintaining calculation speed through efficient time-multiplexed execution.
Solution Approach 2:
The patent merges multiple computational functions into a single arithmetic unit. Instead of having separate hardware resources for matrix-vector multiplication, vector operations, and other tasks, the system combines these functions into one reconfigurable unit. The control unit coordinates this merged resource to handle different task types, reducing overall hardware complexity while maintaining calculation throughput through time-division multiplexing of the shared arithmetic unit.
Data Source
AI summary
A simulator includes an arithmetic unit configured to simulate a technical system. The simulator is configured to determine an output vector for outputting an output signal of the simulator on the basis of an input vector using matrix-vector multiplication. A matrix represents the technical system. The arithmetic unit has at least one multiplier and at least one adder for the matrix-vector multiplication. The at least one multiplier and the at least one adder are each configured for a time-division multiplexing function for performing their respective tasks. A scheduler is provided, which is configured to assign an output value of the at least one multiplier to the at least one adder.