Simultaneous Read Write Calibration for Memory Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Calibrating memory systems with high clock rates and fast edge speeds is challenging due to timing variations and skews, especially in systems with larger memory and wider memory buses, requiring efficient methods to adjust write and read delays across various conditions.
Innovation Solution
A method for simultaneous write and read calibration that involves initial separate checks for read and write delays, followed by shmoo characterization adjustments, allowing for concurrent testing and adjustment of both delays until read and write edges are detected, thereby reducing calibration time and improving system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate read and write calibration checks are performed sequentially, then each delay can be adjusted individually, but the total calibration time increases significantly
Solution Approach 1:
The patent merges separate read calibration and write calibration processes into a single simultaneous calibration operation. The calibration controller executes both read checks and write checks concurrently, adjusting read delay and write delay parameters in the same calibration pass, thereby reducing total calibration time while maintaining individual delay precision.
Solution Approach 2:
The calibration process maintains continuous useful action by performing read and write operations simultaneously rather than sequentially. The calibration controller continuously monitors both read and write delay parameters and adjusts them concurrently, ensuring that calibration activities are maximally utilized without idle time between separate calibration phases.
2Loss of time
If simultaneous write and read calibration is performed, then calibration time is reduced, but the complexity of coordinating both delays increases
Solution Approach 1:
The patent introduces a calibration controller as an intermediary component that manages the simultaneous calibration process. This controller coordinates the timing and parameter adjustment for both read and write operations, handling the complexity of concurrent calibration while presenting a simplified interface to the rest of the memory system.
Solution Approach 2:
The calibration process utilizes parameter changes by systematically varying delay parameters for both read and write operations simultaneously. The calibration controller adjusts these parameters in a coordinated manner, changing multiple parameters in sync to optimize timing while managing the increased complexity through structured parameter management.
3Measurement precision
If initial separate checks are performed before simultaneous calibration, then calibration accuracy is improved, but the overall process time increases
Solution Approach 1:
The patent applies preliminary action by performing initial separate read and write checks before executing the simultaneous calibration process. These preliminary checks establish baseline delay values that serve as starting points for the subsequent simultaneous calibration, improving convergence accuracy while minimizing the time spent in the detailed calibration phase.
Data Source
AI summary
To calibrate an electronic circuit, a calibration controller tests the electronic circuit with an initial separate read check allowing for a read delay and with an initial separate write check allowing for a write delay. The calibration controller, responsive to passing the initial read check and the initial write check, for each condition of a range of conditions, iteratively performs a write test with the write delay concurrent with a read test with the read delay on the electronic circuit over the range of conditions while simultaneously adjusting the write delay and adjusting the read delay for each iteration until one or more of a read edge and a write edge are detected.