Simultaneous Silicidation of Polysilicon Gate and Source/Drain
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices scale down to the nanometer regime, issues such as leakage current, polysilicon gate electrode depletion, and contact resistance reduce transistor drive current, and high-K gate dielectrics face reliability and compatibility problems with polysilicon gate electrodes.
Innovation Solution
A method of simultaneously siliciding the polysilicon gate and source/drain regions of a semiconductor device, using a process flow that includes forming a gate stack with polysilicon and nitride layers, followed by chemical mechanical polishing and simultaneous silicidation, to improve transistor performance while maintaining integrity and avoiding unwanted diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If polysilicon gate electrodes are used in scaled transistors, then device density and switching speed are improved, but contact resistance and polysilicon gate depletion effects increase, reducing drive current
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate electrode by forming a silicide layer (such as nickel silicide) on the polysilicon gate surface. This transformation modifies the surface properties to reduce contact resistance and eliminate polysilicon gate depletion effects, thereby maintaining high drive current while preserving the speed benefits of scaled polysilicon transistors.
Solution Approach 2:
The patent creates a composite gate electrode structure combining polysilicon and silicide materials. The polysilicon provides the necessary work function and gate control, while the silicide layer provides low contact resistance and eliminates depletion effects. This composite approach allows the device to simultaneously achieve high switching speed and reliable drive current in scaled transistors.
2Ease of operation
If separate silicidation processes are performed for gate and source/drain regions, then selective control is achieved, but process complexity and manufacturing steps increase
Solution Approach 1:
The patent merges the silicidation processes for the gate electrode and source/drain regions into a single simultaneous annealing step. By using a unified process approach with appropriately designed masking and deposition, both regions undergo silicidation concurrently, reducing the total number of process steps and simplifying manufacturing while maintaining the necessary selective control over which regions receive the silicide layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor drive current by reducing contact resistance and polysilicon gate electrode issues, maintaining the integrity of transistor operation, and simplifying the process flow by performing silicidation stages concurrently.
Implementation Method 1
performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer
Implementation Method 2
performing a simultaneous silicidation of the first polysilicon layer and the active region
Data Source
AI summary
A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.