SiN Dielectric Layers for GaN HEMT RF Gain
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Solution Overview
Problem
The deposition of a 200-nm silicon nitride (SiN) layer in MMIC fabrication introduces unwanted parasitic capacitances that degrade radio frequency (RF) gain performance in millimeter-wave devices, particularly in gallium nitride (GaN) based high electron mobility transistors (HEMTs), and the existing PECVD process makes it difficult to selectively remove this layer without compromising the passivation layer, leading to surface contamination and leakage currents.
Innovation Solution
A method involving different deposition processes for forming layers with distinct etch rates is used to selectively remove the upper SiN layer while preserving the lower passivation layer, utilizing molecular beam epitaxy (MBE) for the lower layer and PECVD for the upper layer, with the etchant selectively removing the upper layer to minimize RF loading and maintain passivation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If PECVD is used to deposit both Pass-SiN and Cap-SiN layers, then the deposition process is simple and consistent, but selective removal of Cap-SiN becomes extremely difficult and impractical
Solution Approach 1:
The patent applies parameter changes by depositing the Pass-SiN layer with different PECVD parameters (lower temperature, different gas flow ratios, different pressure) compared to the Cap-SiN layer. This creates distinct etch rate characteristics, allowing the Cap-SiN to be selectively removed while preserving the Pass-SiN layer using buffered HF etching.
2Ease of manufacture
If PECVD Pass-SiN is deposited after semiconductor removal from growth apparatus, then the process is simplified, but surface contamination from air exposure increases causing leakage currents
Solution Approach 1:
The patent applies preliminary action by performing in-situ deposition of the Pass-SiN layer immediately after semiconductor layer formation within the growth apparatus, before the system is exposed to air. This prevents surface contamination from occurring in the first place, eliminating the need for subsequent cleaning steps and avoiding leakage currents.
3Strength
If 200-nm Cap-SiN layer is added for MIM capacitors, then capacitor robustness is improved, but RF gain performance deteriorates due to parasitic capacitances
Solution Approach 1:
The patent applies segmentation by dividing the dielectric structure into two distinct layers: a thin Pass-SiN layer (10-50 nm) for passivation and a thicker Cap-SiN layer (200 nm) for capacitor formation. This segmentation allows the Cap-SiN to be selectively removed in non-capacitor regions, eliminating parasitic capacitances that degrade RF gain while preserving the robust capacitor structure where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decouples the capacitor SiN from the passivation SiN, reducing RF loading, minimizing leakage currents, and maintaining high-frequency performance by achieving precise control over dielectric thickness and reducing surface contamination, thereby enhancing the RF gain and power performance of millimeter-wave devices.
Implementation Method 1
forming the material as a lower layer of the structure using a first deposition process... utilizing molecular beam epitaxy (MBE) for the lower layer
Implementation Method 2
forming the upper layer of the structure with the material on the lower using a second deposition process... utilizing PECVD for the upper layer
Implementation Method 3
applying the predetermined etchant to upper layer to selectively remove the upper while leaving the lower layer... providing the upper layer with a second etch rate to the predetermined etchant higher than the first etch rate
Data Source
AI summary
A method for forming a structure on a surface of a semiconductor. The method includes: forming the material as a lower layer of the structure using a first deposition process to provide the lower layer with a first etch rate to a predetermined etchant; forming the upper layer of the structure with the material on the lower using a second deposition process to provide the upper layer with a second etch rate to the predetermined etchant higher than the first etch rate; and applying the predetermined etchant to upper layer to selectively remove the upper while leaving the lower layer.