SiN Epitaxial Blocking Layers for Selective Growth
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Solution Overview
Problem
In semiconductor device fabrication, existing methods face challenges in preventing the interference between epitaxial layers formed in PMOS and NMOS regions during the selective epitaxial growth process, leading to performance issues.
Innovation Solution
The method involves forming epitaxial blocking layers using a nitrogen-containing plasma atmosphere on the semiconductor substrate, specifically forming SiN epitaxial blocking layers on source/drain regions to shield and prevent the growth of epitaxial layers in adjacent regions, allowing for selective epitaxial growth while maintaining an open area for improved gap-filling and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If epitaxial blocking layers are formed to prevent interference between PMOS and NMOS epitaxial layers, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Silicon nitride epitaxial blocking layers are introduced as intermediary materials between the PMOS and NMOS regions. These blocking layers prevent unwanted epitaxial growth in specific regions while allowing growth in other regions, thereby achieving precise control over epitaxial layer formation without requiring complex masking and etching processes
Solution Approach 2:
The invention utilizes changes in plasma composition (introducing nitrogen-containing plasma) and processing conditions to selectively form silicon nitride epitaxial blocking layers. By controlling plasma parameters such as gas flow ratios and power settings, the process achieves region-specific epitaxial growth control with simplified fabrication steps
2Reliability
If selective epitaxial growth is performed to form different epitaxial layers in PMOS and NMOS regions, then device performance is improved, but interference between adjacent regions occurs
Solution Approach 1:
Silicon nitride epitaxial blocking layers serve as intermediary barriers that physically separate the PMOS and NMOS regions during epitaxial growth. These blocking layers prevent diffusion and interference between the different epitaxial layers while maintaining the desired selective growth characteristics in each region
Solution Approach 2:
The silicon nitride epitaxial blocking layers are formed in advance before the selective epitaxial growth process. This preliminary action establishes the necessary barriers to prevent interference during subsequent epitaxial layer formation, ensuring that each region develops its intended structure without contamination or unwanted growth from adjacent regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents interference between epitaxial layers, enhances the gap-filling capability, reduces resistance, and increases the open area for subsequent processes like silicide layer formation and metal contact, thereby improving semiconductor device performance.
Implementation Method 1
forming a SiN first epitaxial blocking layer on first source/drain regions associated with the PMOS transistor region and a second SiN epitaxial blocking layer on second source/drain regions associated with of the NMOS transistor region using a nitridating process that applies a plasma formed in a nitrogen-containing atmosphere to exposed portions of an upper surface of the semiconductor substrate
Implementation Method 2
using at least one selective epitaxial growth (SEG) process, forming a first SiGe epitaxial layer on the first source/drain regions of the PMOS transistor region while shielding the second source/drain regions of the NMOS transistor region with the second SiN epitaxial blocking layer
Data Source
AI summary
A method of fabricating a semiconductor device includes forming gate structures on PMOS and NMOS transistor regions of the semiconductor substrate, forming epitaxial blocking layers on source/drain regions of PMOS and NMOS transistor regions using a nitridation process, then selectively removing one of the epitaxial blocking layers, and using a SEG process to form an epitaxial layer on respective source/drain regions while shielding the other source/drain regions with a remaining epitaxial blocking layer.