SiN-Rich Pre-Oxide Layer for CMP Stop
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing chemical-mechanical polishing (CMP) process for semiconductor substrates is complex, requiring multiple steps and increasing fabrication costs and defect density due to the need for different slurry compositions and stop layers for various layers, which complicates the planarization process.
Innovation Solution
A method involving the formation of a silicon nitride (SiN)-rich pre-oxide layer on a semiconductor layer, followed by an anneal treatment to partially transfer it into a SiN layer and a silicon oxide (SiO) layer, allowing for a single deposition step and using the SiN layer as a sufficient stop layer for planarization, reducing the number of steps in the CMP process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple separate CMP processes are used to polish different layers with different slurry compositions, then polishing precision is improved, but process complexity increases and throughput decreases
Solution Approach 1:
The patent combines multiple separate CMP processes into a single integrated CMP process by forming a composite polishing pad with multiple polishing surfaces, each having different polishing characteristics. This allows different layers to be polished simultaneously in one process step, reducing process complexity while maintaining polishing precision.
Solution Approach 2:
The composite polishing pad is designed to perform multiple polishing functions simultaneously. Different surfaces of the same polishing pad can polish different layers with different slurry compositions, making a single polishing device universal for multiple polishing tasks that previously required separate processes.
2Manufacturing precision
If multiple separate CMP processes are used with different stop layers, then stop surface precision is improved, but fabrication cost increases
Solution Approach 1:
The patent merges multiple stop layer formation processes into a single process by using a composite polishing pad that can selectively stop at different layers simultaneously. This eliminates the need for multiple separate CMP processes with different stop layers, reducing fabrication cost while maintaining stop surface precision.
3Manufacturing precision
If multiple separate CMP processes are used, then planarization accuracy is improved, but cycle time increases
Solution Approach 1:
The patent combines multiple sequential CMP processes into a single parallel process using a composite polishing pad with multiple active surfaces. Different layers are polished simultaneously in one operation, dramatically reducing cycle time while maintaining planarization accuracy through the specialized polishing characteristics of each surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the planarization process by reducing the number of steps without impacting the result, thereby improving throughput and reducing fabrication costs and defect density.
Implementation Method 1
an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a silicon oxide (hereinafter abbreviated as SiO) layer
Implementation Method 2
Chemical-mechanical polishing (hereinafter abbreviated as CMP) is one accepted method of planarization... abrasively remove or polish off the surface of the substrate
Data Source
AI summary
A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.