SiN Waveguide BEOL Integration via Wafer Bonding
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Solution Overview
Problem
Current technologies face challenges in integrating high-speed modulators and SiN waveguides coupled to detectors in SiN-based photonic integrated circuit platforms, particularly due to the incompatibility of high-temperature LPCVD processes with standard BEOL processes.
Innovation Solution
The integration of ultra-low loss SiN waveguides in the BEOL section of integrated optoelectronic devices is achieved through wafer-bonding techniques, allowing LPCVD materials to be deposited on a separate bonding wafer, enabling low, moderate, and high-optical confinement SiN waveguides without thermal impact on the host semiconductor wafer, and using wafer-to-wafer bonding to form interfaces between interconnect layer pairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If LPCVD processes are used to deposit SiN waveguides, then ultra-low loss waveguides are achieved, but high temperatures cause thermal damage to the host semiconductor wafer
Solution Approach 1:
The patent segments the fabrication process into two separate wafers: a host semiconductor wafer containing the integrated circuit and a bonding wafer containing the SiN waveguide layer. This allows independent optimization of each wafer's processing conditions, enabling ultra-low loss waveguides on the bonding wafer without thermal damage to the host wafer.
Solution Approach 2:
The bonding wafer acts as an intermediary carrier that holds the SiN waveguide layer during high-temperature LPCVD deposition. After deposition, the bonding wafer is bonded to the host semiconductor wafer, transferring the pre-fabricated low-loss waveguide structure without exposing the host wafer to high temperatures.
2Adaptability or versatility
If SiN waveguides are integrated in the FEOL section, then monolithic integration is achieved, but thermal processes affect the sensitive electronic components
Solution Approach 1:
The patent divides the device into two functionally separate but physically integrated parts: the FEOL section with electronic components on the host wafer, and the SiN waveguide section on the bonding wafer. This segmentation allows each section to be optimized for its specific function without mutual interference.
Solution Approach 2:
The patent moves the SiN waveguide integration from the traditional planar FEOL/BEOL continuum to a vertical dimension by bonding a separate wafer to the host wafer. This out-of-plane integration approach enables waveguide incorporation without affecting the thermal processing of the host wafer's electronic components.
3Ease of manufacture
If standard BEOL processes are used, then compatibility with existing technology is maintained, but integration of ultra-low loss SiN waveguides is not possible
Solution Approach 1:
The patent performs preliminary fabrication of the SiN waveguide layer on the bonding wafer using LPCVD before bonding to the host wafer. This preliminary action on a separate wafer allows the use of high-temperature processes that would otherwise be incompatible with standard BEOL processing on the host wafer.
Solution Approach 2:
The bonding wafer serves as an intermediary that bridges the gap between LPCVD waveguide fabrication and standard BEOL processes. The waveguide is pre-fabricated on this intermediary wafer under optimal conditions, then transferred to the host system through wafer bonding, maintaining compatibility with existing manufacturing workflows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of ultra-low loss SiN waveguides in the BEOL section, reducing propagation losses and allowing for efficient coupling with fast Ge photodetectors, thereby enhancing the opto-electrical bandwidth and compatibility with standard silicon technologies.
Implementation Method 1
such low loss SiN waveguides may require low pressure chemical vapour deposition (LPCVD) materials which are deposited at temperatures well above 700 °C
Implementation Method 2
a wafer-to-wafer bonding interface is formed between a first of the interconnect layer pairs and a second of the interconnect layer pairs
Data Source
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AI summary
The present invention relates to a semiconductor structure comprising a semiconductor wafer and a photonic integrated circuit or an electronic-photonic integrated circuit, hereinafter commonly referred to as integrated circuit, on the semiconductor wafer. The integrated circuit comprises a front-end-of-line section, hereinafter FEOL section, and comprises a back-end-of-line section, hereinafter BEOL section, with interconnect layer pairs each comprising a metal interconnect layer and an interlevel dielectric layer. A wafer-to-wafer bonding interface between a first of the interconnect layer pairs and a second of the interconnect layer pairs is arranged closer to the FEOL section than the first interconnect layer pair or a wafer-to-wafer bonding interface is formed between the first of the interconnect layer pairs and the FEOL section. The first interconnect layer pair comprises at least one SiN waveguide.