SiN Capping Layer for MRAM Top Electrode Etch Control
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Solution Overview
Problem
The process of etching MRAM cells for array connection is challenging due to over-etching of tantalum (Ta) in the top electrode, leading to Ta residue defects that impact device performance during electrical testing.
Innovation Solution
A capping layer, specifically silicon nitride (SiN) formed to a thickness of 30 nm to 50 nm, is applied over a portion of the top electrode to prevent over-etching and residue defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If etching is performed to connect MRAM array, then array connection is achieved, but over-etching occurs causing Ta residue defects
Solution Approach 1:
A capping layer is formed over the top electrode before the etching process to prevent over-etching. This preliminary protective action ensures that the etching process can proceed to achieve array connection without causing Ta residue defects, as the capping layer acts as a barrier that stops the etch at the appropriate depth.
Solution Approach 2:
The capping layer serves as an intermediary element between the etching process and the top electrode. It mediates the interaction by providing a controlled interface that allows the etch to proceed safely without directly attacking the top electrode material, thereby preventing Ta residue formation while still enabling array connection.
2Productivity
If etching is performed to connect MRAM array, then array connection is achieved, but device performance deteriorates due to Ta residue
Solution Approach 1:
The capping layer is applied in advance to protect the top electrode during the array connection etching process. This preliminary protection prevents Ta residue defects that would otherwise deteriorate device performance, allowing both array connection and reliable device operation to be achieved.
Solution Approach 2:
The capping layer, which adds an extra material layer that could be seen as increasing process complexity, actually converts the potential harm of over-etching into a benefit by enabling cleaner etching. The capping layer is subsequently removed, leaving no residue and improving device performance while maintaining array connection capability.
3Manufacturing precision
If capping layer is formed to prevent over-etching, then Ta residue defects are reduced, but process complexity increases
Solution Approach 1:
Instead of attempting to perfectly control the etching process to stop exactly at the desired depth, the capping layer provides a deliberate excess protection that is later removed. This approach trades a simple additional deposition and removal step for the complexity of precise etch control, ultimately simplifying the overall process while improving etch control and reducing Ta residue defects.
Data Source
AI summary
A device including a capping layer over a portion of a top electrode, and method of production thereof. Embodiments include an MRAM cell in a first region and a logic area in a second region of a substrate, wherein the MRAM cell includes a MTJ pillar between a top electrode and a bottom electrode; and a capping layer over a portion of the top electrode.