Single-ADC Quadrature Signal Processing for I/Q Phase Matching

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Solution Overview

Problem

Conventional quadrature signal RF receivers require two separate ADC units to convert I and Q channels, leading to challenges in matching operational characteristics, which results in increased system size, cost, and degraded performance due to ADC unit variations.

Innovation Solution

A single ADC unit is used to digitize both I and Q channels in an interleaved manner, with digital post-processing to compensate for phase-mismatch, and digital filters to reconstruct quadrature signals, eliminating the need for separate ADC units and reducing system size and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If two separate ADC units are used to convert I and Q channels, then conversion capability is improved, but system size and cost increase

Engineering Contradiction:
Improveconversion capabilityVSAvoidsystem size
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent combines two separate ADC units into a single ADC unit that processes both I and Q channels sequentially. The I/Q receiver uses one ADC to convert alternating samples from the in-phase and quadrature channels, eliminating the need for two separate ADC units while maintaining the conversion capability for both channels.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single ADC unit is designed to perform multiple functions by sequentially converting samples from both I and Q channels. The ADC serves as a universal converter that handles both channel types through time-division multiplexing, making one component perform the work of what would traditionally require two separate components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If two separate ADC units are used to convert I and Q channels, then conversion capability is improved, but manufacturing cost increases

Engineering Contradiction:
Improveconversion capabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent merges two separate ADC units into one, directly reducing component count and associated manufacturing costs. By combining the conversion function for both I and Q channels into a single ADC unit, the system eliminates the need to manufacture, test, and assemble two separate ADC components.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single ADC unit provides universal conversion capability for both I and Q channels, reducing the total number of specialized components needed. This multi-functionality approach lowers manufacturing costs by requiring fewer discrete ADC units while maintaining full conversion capability for both signal channels.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If two separate ADC units are used to convert I and Q channels, then conversion capability is improved, but performance degrades due to ADC unit variations

Engineering Contradiction:
Improveconversion capabilityVSAvoidperformance consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent combines both I and Q channel conversions into a single ADC unit, ensuring that both channels use identical conversion characteristics. Since the same physical ADC unit processes both channels sequentially, there are no manufacturing variations or mismatches between separate ADC units, improving gain and phase matching consistency.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system achieves homogeneity in conversion characteristics by using a single ADC unit for both I and Q channels. The identical conversion process applied to both channels eliminates the heterogeneity and variations that would exist between two separate ADC units, ensuring consistent performance across both signal paths.

Inventive Principle:
Principle #33Homogeneity

4Area of stationary object

If a single ADC unit is used to digitize both I and Q channels, then system size is reduced, but phase-mismatch occurs

Engineering Contradiction:
Improvesystem sizeVSAvoidphase accuracy
Core Design Contradiction:
Area of stationary objectVSMeasurement precision

Solution Approach 1:

The patent implements digital post-processing that measures and compensates for phase-mismatch introduced by the single ADC unit. By detecting the phase error and applying corrective processing to the digitized samples, the system maintains accurate quadrature relationships despite the sequential sampling inherent in using a single ADC.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system changes parameters in the digital domain to correct for phase-mismatch. By adjusting phase and gain parameters during digital post-processing, the system compensates for the timing differences introduced by alternating between I and Q channel samples, restoring accurate quadrature relationships.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4576588A1Quadrature signal processor using single analog-to-digital converter unit
Publication Date: 2025.06.25 NXP BV
  • EP4576588A1 patent drawingFigure 1
  • EP4576588A1 patent drawingFigure 2~3
  • EP4576588A1 patent drawingFigure 4~5

AI summary

A system and method to process received quadrature signals is presented. A received signal is processed into in-phase and quadrature components. A multiplexer alternately outputs the analog in-phase component signal and the analog quadrature component signal at the output terminal as a multiplexer output signal. An analog-to-digital converter digitizes the signals. A demultiplexer is configured to receive the digital output stream, and, at a frequency determined by a second control signal, alternately output the digital output stream at a first output terminal of the demultiplexer as a digital representation of the in-phase component signal and a second output terminal of the demultiplexer as a digital representation of the quadrature component signal. A filter system is configured to impose a one-half sampling period delay on at least one of the digital representation of the in-phase component signal and the digital representation of the quadrature component signal.