Single-ADC Quadrature Signal Processing With Phase-Mismatch Compensation
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Solution Overview
Problem
Conventional quadrature signal receivers require two separate ADC units for I and Q channels, leading to challenges in matching operational characteristics, which increases system cost, size, and current consumption, and introduces performance degradation.
Innovation Solution
A single ADC unit is used to digitize both I and Q channels in an interleaved manner, with digital post-processing to compensate for phase-mismatch, and digital filters to reconstruct quadrature signals, eliminating the need for separate ADC units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two separate ADC units are used to convert I and Q channels, then conversion capability is improved, but system cost, size, and current consumption increase
Solution Approach 1:
The patent combines two separate ADC units into a single ADC unit that processes both I and Q channels. The in-phase and quadrature component signals are multiplexed into a single analog signal stream that is fed to one ADC, eliminating the need for duplicate converter hardware while maintaining full conversion capability for both channels.
Solution Approach 2:
A single ADC unit is designed to perform the conversion function for both I and Q channels universally. The ADC is configured to receive multiplexed input signals and convert them, serving multiple functions that previously required separate dedicated units, thereby reducing overall system complexity.
2Adaptability or versatility
If two separate ADC units are used for I and Q channels, then channel independence is improved, but matching operational characteristics becomes difficult
Solution Approach 1:
By merging the conversion function into a single ADC unit, the patent eliminates the operational characteristic mismatch problem entirely. Since both I and Q channels are converted by the same hardware unit, issues such as gain mismatch, offset mismatch, and distortion variations between separate ADCs are completely avoided.
Solution Approach 2:
The patent ensures homogeneous conversion conditions for both I and Q channels by using the same ADC unit. The multiplexed signal path and single converter architecture guarantee that both channels experience identical operational characteristics, eliminating heterogeneity-induced performance degradation.
3Device complexity
If a single ADC unit is used to digitize both I and Q channels, then system cost and size are reduced, but phase-mismatch issues are introduced
Solution Approach 1:
The patent introduces a feedback mechanism where the digitized I and Q signals undergo digital signal processing that compensates for phase-mismatch. The system measures or estimates the phase error and applies corrective processing in the digital domain to restore accurate quadrature relationships.
Solution Approach 2:
Digital signal processing functions serve as an intermediary between the single ADC conversion and the final I/Q output. This intermediary processing layer corrects phase-mismatch artifacts introduced by the time-division multiplexed conversion, effectively mediating the transition from single-ADC input to accurate quadrature output.
4Ease of manufacture
If ADC units are reduced from two to one, then manufacturing cost is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces the physical hardware solution (two separate ADCs with precise matching) with a digital signal processing solution. Instead of relying on precise manufacturing matching of analog components, the system uses digital algorithms to achieve the required precision, thereby reducing manufacturing cost while maintaining or improving signal accuracy.
Data Source
AI summary
A system and method to process received quadrature signals is presented. A received signal is processed into in-phase and quadrature components. A multiplexer alternately outputs the analog in-phase component signal and the analog quadrature component signal at the output terminal as a multiplexer output signal. An analog-to-digital converter digitizes the signals. A demultiplexer is configured to receive the digital output stream, and, at a frequency determined by a second control signal, alternately output the digital output stream at a first output terminal of the demultiplexer as a digital representation of the in-phase component signal and a second output terminal of the demultiplexer as a digital representation of the quadrature component signal. A filter system is configured to impose a one-half sampling period delay on at least one of the digital representation of the in-phase component signal and the digital representation of the quadrature component signal.


