Single-Address Event Slot Interface for SoC Power State Management
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Solution Overview
Problem
System-on-chip (SoC) designs face complexity in managing multiple power islands and tasks, leading to potential CPU overload and system delays, necessitating a more efficient and flexible power management solution that can operate independently of the CPU.
Innovation Solution
A lightweight power management unit (PMU) IC with a state machine and communications interface that allows for efficient power state management, event handling, and software-hardware interactions, using a single-thread sequential interpreter and event queue to manage power domains and respond to events without overloading the CPU.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a CPU is used to manage tasks and power islands in SoC systems, then system management capability is improved, but the CPU becomes overloaded leading to system delays
Solution Approach 1:
The patent segments the system management functions by introducing a dedicated state machine to handle power island and task management, separating these responsibilities from the CPU. This allows the CPU to focus on computational tasks while the state machine independently manages power domains, preventing CPU overload and system delays.
2Ease of operation
If individualised approaches are used to tailor process management to specific system requirements, then operation of that particular system is improved, but the approach becomes inapplicable to other systems
Solution Approach 1:
The patent implements a universal state machine architecture with configurable parameters that can adapt to different SoC requirements. The state machine uses a standardized interface with configurable power domains, event handlers, and transition rules, allowing the same hardware structure to serve multiple system types from IoT platforms to complex multimedia systems without customization.
3Use of energy by moving object
If multiple power islands are managed in SoC designs, then power efficiency is improved, but complexity in managing power islands increases
Solution Approach 1:
The patent introduces a state machine as an intermediary between the CPU and multiple power islands. This mediator simplifies the management complexity by providing a unified control interface and automated state transition logic, eliminating the need for complex software management of multiple power domains while maintaining power efficiency benefits.
Data Source
AI summary
A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.