Single-Bit Error-Correction Circuit Using Row-Column Parity

The patent segments the data into a two-dimensional array structure with rows and columns, allowing separate parity computation for each dimension. This segmentation enables the use of simpler Hamming codes in each dimension while achieving robust two-dimensional error correction capability, thus maintaining reliability while reducing hardware complexity compared to implementing full BCH codes.

The patent pre-computes and stores syndrome-to-error-location mappings in lookup tables during system initialization or fabrication. During actual decoding operations, the system simply performs a table lookup based on the computed syndrome, achieving O(1) decoding time. This preliminary action eliminates the need for iterative syndrome computation and comparison that plagues the Meggitt decoder, thus dramatically reducing decoding time while keeping the runtime hardware simple.

The patent divides the lookup table into two separate smaller tables: one for row syndromes and one for column syndromes. Each table only needs to store mappings for one dimension's syndrome space. This segmentation reduces the total storage requirement from needing to store all possible two-dimensional error patterns to storing only the product of the square roots, i.e., sqrt(M*N) instead of M*N entries, thus achieving fast decoding with reduced storage.

The patent implements a self-service bootstrapping mechanism where a simple hardware error correction circuit using the two-dimensional array method provides basic error correction during device startup and software loading. Once the software is loaded into memory, the system transitions to using the more capable software-based BCH decoder for subsequent operations. This self-service approach allows the device to be fully functional from power-on without external assistance, while still achieving robust error correction.