Single Buffer Data Transformation for Embedded Systems

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Solution Overview

Problem

Existing data transformation methods in electronic systems require intermediate buffers, which are resource-intensive and undesirable in embedded computing systems, where data needs to be transformed from one order to another, such as from raster/line order to block order, necessitating the use of multiple buffers to avoid overwriting memory.

Innovation Solution

A method and apparatus that allow data transformation using a single buffer by writing data to memory in the source order and reading it in the preferred order, enabling continuous filling and refilling of memory without waiting for the entire memory to be read or processed, utilizing a single memory size equal to the product of the number of rows and block size, and calculating write and read addresses using specific increments to ensure efficient data access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple buffers are used to avoid overwriting memory during data transformation, then data integrity is maintained, but resource usage increases

Engineering Contradiction:
Improvedata integrityVSAvoidmemory resources
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent implements dynamic buffer management where a single buffer is reused across multiple transformation cycles. The buffer transitions between being a source buffer and a destination buffer in alternating operations, allowing continuous data transformation without requiring multiple static buffers. This dynamic reuse maintains data integrity through controlled access patterns while reducing memory resource consumption from multiple buffers to a single reusable buffer.

Inventive Principle:
Principle #15Dynamics

2Reliability

If data is read from memory only after complete writing, then data consistency is ensured, but processing efficiency decreases

Engineering Contradiction:
Improvedata consistencyVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements preliminary action by pre-calculating and storing transformation parameters (such as block size, line length, and address mapping relationships) before the actual data transformation begins. This allows the system to establish the transformation framework in advance, enabling subsequent data transformations to proceed efficiently without real-time calculation overhead while maintaining data consistency through pre-validated transformation logic.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables continuous useful action by implementing overlapping data transformation operations where writing and reading operations are interleaved rather than sequential. The system continuously transforms data through alternating read and write operations on the same buffer, eliminating idle waiting time and maintaining continuous productive action while ensuring data consistency through controlled buffer access patterns.

Inventive Principle:
Principle #20Continuity of useful action

3Quantity of substance

If a single buffer is used for data transformation, then resource usage is reduced, but the risk of overwriting unread data increases

Engineering Contradiction:
Improvememory resourcesVSAvoiddata safety
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies segmentation by dividing the data transformation process into distinct operational phases (read phase and write phase) that are executed in alternating sequence. The single buffer is segmented in time rather than space, with each phase having exclusive access rights. This temporal segmentation prevents overwriting of unread data by ensuring that write operations only occur after corresponding read operations are complete, while still using only a single buffer for transformation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11157208B2Methods and apparatus for improving data transformation in processing devices
Publication Date: 2021.10.26 MOVIDIUS LTD
  • US11157208B2 patent drawing
  • US11157208B2 patent drawing
  • US11157208B2 patent drawing

AI summary

An example apparatus includes a memory, a data writer to write received first data into the memory in a first order, and a data reader to read the first data from the memory in a second order, wherein the data writer is to write second data into the memory in the second order.