Single-Capacitor CMOS Relaxation Oscillator for Low-Frequency Clocks
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Solution Overview
Problem
Designing CMOS relaxation oscillators that require minimal chip area, achieve a reliable duty cycle, and prevent substrate leakage or latch-up, while operating at low frequencies and small technology nodes is challenging.
Innovation Solution
A CMOS relaxation oscillator design utilizing a single capacitive element, a comparator, logic circuitry, and a switching network that alternates between two symmetrical phases, with the switching network configured to operate nodes between positive and negative potentials without causing substrate leakage or latch-up, using a single current source and a threshold detection unit to manage voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a conventional CMOS relaxation oscillator design is used, then the circuit can oscillate, but it requires large chip area and cannot operate at low frequencies
Solution Approach 1:
The patent merges the functions of multiple capacitive elements into a single capacitive element by utilizing both terminals of the capacitor for charging and discharging operations. This consolidation reduces the total chip area required while maintaining the oscillation functionality through coordinated switching of both capacitor terminals between positive and negative potentials.
Solution Approach 2:
The patent implements dynamic voltage switching where the capacitor terminals alternate between positive and negative potentials relative to ground supply. This dynamic operation allows the single capacitor to perform multiple functions (charging, discharging, voltage inversion) that would traditionally require separate static components, enabling low-frequency operation with minimal area.
2Area of moving object
If nodes are switched between positive and negative potentials, then area is reduced, but substrate leakage and latch-up risks increase
Solution Approach 1:
The patent introduces a virtual ground voltage as an intermediary reference level for the capacitor terminals. Instead of directly switching between positive and negative potentials relative to actual ground, the terminals switch relative to this virtual ground, which is maintained at a safe voltage level. This intermediary approach enables area-efficient switching while preventing direct negative potential connections to substrate that would cause leakage or latch-up.
Solution Approach 2:
The patent applies different voltage reference qualities to different parts of the circuit. The capacitor terminals operate with dynamic potentials relative to virtual ground, while the virtual ground itself is maintained at a stable, safe voltage level relative to actual ground. This local differentiation allows aggressive voltage switching where needed while maintaining substrate safety where critical.
3Reliability
If multiple capacitive elements are used, then duty cycle reliability improves, but chip area increases
Solution Approach 1:
The patent combines the duty cycle control functions that would traditionally require multiple separate capacitive elements into a single capacitor by utilizing both of its terminals. Through coordinated switching of both terminals and the use of virtual ground, the circuit achieves reliable duty cycle control equivalent to multi-capacitor designs while occupying minimal chip area.
Data Source
AI summary
Methods and circuits for CMOS relaxation oscillators are disclosed. A single capacitive element, a single current source and a switching network are utilized. A switching network of the oscillator allows both nodes of the capacitive element to rise and fall between a positive and a negative voltage with respect to ground supply, without causing leakage to substrate or risk of latch-up, i.e. the inadvertent creation of a low-impedance path. The oscillator requires minimum silicon area, has an improved duty cycle, is particular useful for implementing lower frequency clocks and is enabled for smaller technology nodes, lower than 250 nm, due to lower supply voltage.