Single-Carrier Receiver Decimation Phase Selection for Better Equalization
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Solution Overview
Problem
In single-carrier transmission with frequency equalization, the choice of decimation phase in the receiver affects signal quality, leading to signal degradation and suboptimal symbol detection due to the need for oversampling and hardware resource constraints, particularly when the Fast Fourier Transform (FFT) length is not a power of two, making it challenging to implement frequency domain decimation effectively.
Innovation Solution
A method that extracts decimation assistance samples and useful samples from the filtered signal frame, estimates the variance of each decimation phase, identifies the phase with the minimum variance, and decimates the signal by a factor drx, ensuring the equalizer receives samples at the optimal sampling frequency B, thereby improving symbol detection performance and bit error rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oversampling is performed to avoid signal degradation from improper decimation phase, then signal quality is improved, but hardware resource requirements and processing complexity increase
Solution Approach 1:
The patent performs preliminary estimation of decimation phase variance using a subset of samples before full signal processing. By pre-determining the optimal decimation phase from filtered signal frames, the system avoids the need for continuous oversampling and complex real-time phase adjustment, thereby reducing hardware resource requirements while maintaining signal quality
Solution Approach 2:
The patent extracts only the necessary information (variance estimation from selected samples) to determine the optimal decimation phase, rather than processing the entire signal at oversampled rates. This extraction approach allows the system to identify the correct decimation phase using minimal computational resources, resolving the contradiction between signal quality and hardware complexity
2Adaptability or versatility
If FFT length is not a power of two, then flexibility in processing is improved, but implementation complexity and computational burden increase
Solution Approach 1:
The patent implements a self-adjusting decimation phase selection mechanism that automatically determines the optimal phase based on variance estimation from the received signal. This self-service approach allows the system to adapt to different FFT lengths (whether power of two or not) without requiring complex external control logic or pre-computed lookup tables, thereby maintaining flexibility while reducing implementation complexity
Solution Approach 2:
The patent changes the parameter being optimized from fixed decimation phase to variable decimation phase selected based on signal characteristics. By estimating variance for different decimation phases and selecting the optimal one, the system adapts to different FFT lengths and signal conditions, achieving flexibility without proportionally increasing implementation complexity
3Productivity
If decimation is performed to reduce sampling rate to B, then processing efficiency is improved, but signal degradation occurs due to incorrect decimation phase
Solution Approach 1:
The patent implements a feedback mechanism where the variance of decimation phases is estimated from the received signal, and this information is used to select the optimal decimation phase before full signal processing. This feedback loop ensures that decimation is performed with the correct phase, maintaining symbol detection performance while achieving the desired processing efficiency through rate reduction to B
Solution Approach 2:
The patent performs preliminary variance estimation and decimation phase identification before the main equalization and detection processes. By determining the optimal decimation phase in advance from filtered signal frames, the system ensures that subsequent decimation to rate B does not cause signal degradation, thereby maintaining reliability while improving productivity
Data Source
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AI summary
A processing method in a wireless telecommunications receiver (6) receiving a digitally modulated single-carrier signal comprises, between a time-domain matched filter (6_2) operating at a frequency drx×B and a frequency equalizer (6_3) operating at frequency B, a decimation step comprising: i/ extraction, from a filtered signal frame, of a first sequence of samples to aid decimation and of the same power; and of a second sequence of useful samples intended to be equalized; ii/ estimation of the variance of the power of each of the drx decimation phases of the first sequence and identification of the nth decimation phase associated with the minimum variance; iii/ decimation of the second sequence by selection of the nth decimation phase of the second sequence and supplying, as input to the frequency equalizer, said decimation phase.