Single-Carrier Receiver Decimation Phase Selection for Symbol Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In single-carrier wireless telecommunications, the selection of an appropriate decimation phase is crucial to avoid signal degradation due to frequency gaps and ensure perfect detection, but existing methods are costly in terms of hardware resources and require complex computations, especially when the downsampling factor is not a power of 2.

Innovation Solution

A method that involves extracting sequences of samples from a filtered signal frame, estimating the variance of each decimation phase, identifying the phase with the minimum variance, and decimating the payload samples by the identified phase to ensure optimal sampling frequency, thereby improving symbol detection performance and reducing bit error rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If FFT algorithm is used for frequency domain equalization, then processing efficiency is improved, but hardware complexity increases and implementation becomes difficult when sampling frequency is not a power of two

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidhardware complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent changes the parameter of sampling frequency representation by introducing an oversampling factor L, transforming the original sampling frequency fs into L×fs. This parameter transformation enables the use of FFT algorithms even when the original sampling frequency is not a power of two, thereby improving processing efficiency while avoiding the hardware complexity of implementing FFT with non-power-of-two frequencies.

Inventive Principle:
Principle #35Parameter changes

2Speed

If decimation is performed without proper phase selection, then signal processing speed is improved, but signal degradation occurs due to frequency gaps

Engineering Contradiction:
Improvesignal processing speedVSAvoidsignal quality
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by performing phase optimization before the decimation process. The system evaluates multiple candidate phases and selects the optimal phase that minimizes signal degradation before actually performing the decimation operation. This preliminary phase selection ensures that when decimation is performed to improve processing speed, the signal quality is preserved by avoiding frequency gaps through proper phase alignment.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If multiple decimation phases are evaluated to find optimal phase, then symbol detection performance is improved, but computational complexity increases

Engineering Contradiction:
Improvesymbol detection accuracyVSAvoidcomputational complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies partial action by evaluating only a limited set of candidate phases (typically L phases where L is the oversampling factor) rather than exhaustively searching all possible phases. This partial evaluation approach achieves sufficient symbol detection accuracy by considering the most relevant phases while avoiding the excessive computational complexity of a complete phase search, thus finding an optimal balance between detection performance and computational load.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12184457B2Processing method in a wireless telecommunications receiver receiving a digitally modulated single-carrier signal, associated wireless telecommunications receiver and associated computer program
Publication Date: 2024.12.31 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
  • US12184457B2 patent drawing
  • US12184457B2 patent drawing
  • US12184457B2 patent drawing

AI summary

A processing method in a wireless telecommunications receiver receiving a digitally modulated single-carrier signal includes, between a matched filter, in the time domain, operating at a frequency drx×B and a frequency equalizer, operating at the frequency B, a decimation step comprising: i/extracting, from a filtered signal frame, a first sequence of samples for aiding the decimation and having the same power; and a second sequence of payload samples intended to be equalized; ii/estimating the variance in the power of each of the drx decimation phases of the first sequence and identifying the nth decimation phase associated with the minimum variance; iii/decimating the second sequence by selecting the nth decimation phase of the second sequence and supplying the decimation phase at the input of the frequency equalizer.