Single-Chamber Semiconductor Etching for Low-Contamination Mask Removal
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Solution Overview
Problem
As semiconductor devices approach smaller feature sizes, the processes used in their manufacturing face challenges such as the need for precise etching and removal of hardmasks and etch stop layers, which can lead to inefficiencies and contamination issues in current multi-step processes.
Innovation Solution
A single-chamber process using selective etchants and rinses to remove both hardmasks and etch stop layers, with controlled dispensing and rotation of the semiconductor device to achieve precise etching and minimize contamination, allowing for smoother sidewalls and tighter spacing between features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-step processes are used to remove hardmasks and etch stop layers, then removal can be achieved, but contamination risks increase and process throughput decreases
Solution Approach 1:
The patent combines multiple etching steps and rinsing operations into a single etching chamber, eliminating the need to transfer substrates between different process chambers. This merging of processes reduces contamination risks from substrate handling while maintaining high process throughput through continuous operation within one chamber.
Solution Approach 2:
The etching chamber is designed to perform multiple functions: removing hardmasks, removing etch stop layers, and performing intermediate rinsing operations. This multi-functional capability allows all necessary process steps to be completed in one location, improving both reliability and productivity.
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but etching precision requirements increase and process challenges arise
Solution Approach 1:
The patent employs selective etchants that act differently on different materials (hardmask vs. etch stop layer) at different locations on the substrate. This localized chemical selectivity enables precise removal of specific layers without affecting adjacent features, meeting the increased precision requirements for smaller feature sizes.
Solution Approach 2:
The process utilizes controlled changes in etchant concentration, temperature, and exposure time to achieve precise etching at reduced feature sizes. By adjusting these parameters, the process maintains manufacturing precision while supporting higher integration density.
3Ease of manufacture
If hardmasks and etch stop layers are removed using conventional processes, then material removal is achieved, but sidewall smoothness deteriorates and feature quality decreases
Solution Approach 1:
The patent introduces intermediate rinsing steps using the etching chamber as a mediator between etching operations. These rinsing steps remove reaction byproducts and prevent redeposition on sidewalls, maintaining smooth feature geometry while efficiently removing hardmasks and etch stop layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances process throughput, reduces contamination risks, and achieves smoother etched features by performing all necessary etching and rinsing steps within a single apparatus, improving the efficiency and precision of semiconductor device manufacturing.
Implementation Method 1
applying a first etchant to remove the hard mask layer
Implementation Method 2
applying a second etchant to remove a portion of the etch stop layer
Data Source
AI summary
An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.