Single Channel Memory Controller for HBM Pseudo Channel Mode
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional high-bandwidth memory (HBM) systems require separate architectures to support both pseudo channel mode and legacy mode, leading to increased hardware resource usage, power consumption, and asynchronous operation of pseudo channel subcontrollers, which limits system performance and compatibility.
Innovation Solution
Implementing a single command channel and single data channel architecture that uses pseudo channel rotation to map user addresses to DRAM memory in a contiguous block, eliminating duplicated command traffic logic and improving synchronization between pseudo channel traffics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional pseudo channel mode architecture is used, then pseudo channel mode is supported, but legacy mode compatibility is lost and hardware resources are doubled
Solution Approach 1:
The memory controller is designed with a single command channel and single data channel architecture that can universally support both legacy mode and pseudo channel mode operations. The controller uses mode selection signals to configure the same hardware resources for different operational modes, eliminating the need for separate dedicated controllers for each mode and reducing overall system complexity while maintaining versatility.
Solution Approach 2:
The controller dynamically reconfigures its internal signal routing and control logic based on the selected operational mode. In pseudo channel mode, the single command channel is divided into two virtual sub-channels with independent data paths, while in legacy mode, the full data width is used. This dynamic adaptation allows the same physical architecture to serve multiple functions without requiring duplicated hardware.
2Ease of operation
If two separate command channels are used for pseudo channel mode, then each pseudo channel can operate independently, but control logic area and power consumption increase
Solution Approach 1:
The invention merges the command control logic for both pseudo channels into a single shared command channel. Instead of having separate command generators and control logic for each pseudo channel, the system uses one unified command channel that services both virtual channels through time-division multiplexing. This reduces the total area of control logic and decreases power consumption by eliminating redundant circuitry while maintaining the operational independence of each pseudo channel.
Solution Approach 2:
The controller introduces an intermediary command arbitration mechanism that manages access to the shared command channel. This arbitration logic ensures that commands for different pseudo channels are properly timed and sequenced, allowing independent operation of each pseudo channel while sharing common command infrastructure. The intermediary layer coordinates the timing and routing of commands to prevent conflicts and maintain synchronization.
3Reliability
If duplicated command traffic logic is used for pseudo channel mode, then each pseudo channel has dedicated control logic, but device area increases
Solution Approach 1:
The controller segments the data path into separate virtual channels for pseudo channel mode operations, but shares the command control logic across both segments. The data paths are divided to provide independent 64-bit wide channels, while the command channel remains unified and is time-multiplexed between the two virtual channels. This segmentation approach maintains the reliability and independence of each pseudo channel while avoiding the need to duplicate the entire command control logic, thereby reducing overall die area.
4Productivity
If separate port command buffers and command queues are used for each pseudo channel, then each channel can buffer commands independently, but command path duplication increases complexity
Solution Approach 1:
The controller implements a single command buffer and single command queue that serve both pseudo channels universally. Instead of having separate buffering structures for each channel, the system uses one shared buffer that stores commands for both virtual channels and processes them through a unified command path. This multi-functional approach maintains adequate command buffering capacity to handle traffic for both channels while eliminating the complexity of duplicated command paths and reducing overall resource consumption.
Data Source
AI summary
Embodiments of the invention provide an approach to implement a single architecture to support high bandwidth memory of pseudo channel mode or legacy channel mode by using a single command channel and single data channel. An address mapping method forces each port transaction to alternatively split to two pseudo channels. Compared to the conventional pseudo channel architecture, the single architecture and pseudo channel rotation eliminates the need for duplicated command traffic logic, and a time division command arbitrator, which greatly reduces both control logic and power consumption of the circuits. Furthermore, pseudo channel rotation improves the utilization of memory bandwidth because the address mapping improves synchronization of the two pseudo channel traffics.