Single-Channel Clock-Data Encoding With Long-Short Pulse Codes
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Solution Overview
Problem
Existing single-channel communication methods require multiple isolated channels for data and clock transmission, leading to high power consumption, increased wafer cost, and complex clock-data recovery circuits that struggle with long strings of '0' or '1' signals, deviated data code rates, and prolonged communication establishment times.
Innovation Solution
A method and circuit for encoding and decoding that combines clock and data signals into long- and short-code signals with different duty cycles, allowing for efficient single-channel communication by generating delay clock signals and selecting between long- and short-code signals based on data signals, thereby reducing circuit complexity and wire bonding requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two isolated channels are used for data and clock transmission, then communication reliability is improved, but power consumption increases and wafer cost increases
Solution Approach 1:
The patent combines data signal and clock signal into a single long- and short-code signal transmitted through one isolated channel. The encoder merges the data signal and clock signal by generating long-code signals for data '1' and short-code signals for data '0', both synchronized with the clock, thereby reducing power consumption and wafer cost while maintaining communication reliability through single-channel transmission.
2Ease of manufacture
If clock-data recovery circuit is used for single-channel communication, then wire bonding cost is reduced, but communication establishment time increases and circuit complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the long- and short-code signal with the clock signal at the transmitter side. The encoder generates coded signals that are already synchronized with the clock, allowing the receiver to directly decode and recover the clock signal without requiring complex clock-data recovery circuits with phase-locked loops, thereby reducing communication establishment time and circuit complexity.
3Productivity
If long strings of '0' or '1' signals are transmitted, then data transmission capability is improved, but clock-data recovery circuit performance deteriorates
Solution Approach 1:
The patent applies asymmetry by using different pulse widths for representing data '1' (long-code signal) and data '0' (short-code signal). This asymmetric encoding ensures that the signal always contains clock synchronization information through the consistent pulse width relationship, preventing the loss of clock edges that occurs with long strings of identical data values in conventional encoding schemes, thereby maintaining clock-data recovery performance while enabling high-speed data transmission.
4Adaptability or versatility
If data code rate is deviated from VCO frequency, then encoding flexibility is improved, but locking time increases
Solution Approach 1:
The patent applies feedback by using the clock signal itself as the timing reference for encoding data. The encoder generates long- and short-code signals that are synchronized with the clock signal, creating an inherent feedback mechanism where the transmitted signal contains its own timing information. This eliminates the need for separate VCO frequency locking and phase locking stages, reducing locking time while maintaining encoding flexibility.
Data Source
AI summary
The present invention relates to a single-channel communication encoding method and decoding method, an encoding circuit, and a decoding circuit. The single-channel communication encoding method comprises: synthesizing a clock signal and a data signal into a long-short code signal, wherein the long-short code signal comprises a long code signal and a short code signal, the pulse width of the long code signal is consistent with that of the clock signal, the pulse width of the short code signal is consistent with that of the clock signal, and the duty ratio of the long code signal and the short code signal is different. According to the present encoding method, the clock signal and the data signal are encoded at the same time, the complexity of the circuit can be reduced, and packaging and wiring of a chip can be reduced.