Single Channel Receiver for Low Power BLE 5.0
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Solution Overview
Problem
Conventional FSK/MSK I/Q receivers require complex analog signal processing, leading to high power consumption due to the need for two processing branches, which is not reduced by smaller process technologies, and struggle to efficiently handle frequency modulated signals, especially in compliance with low-power standards like BLE 5.0.
Innovation Solution
A single channel receiver that shifts complex-valued information to either the real or imaginary part of the analog input signal, allowing for recovery using a single channel, reducing power consumption by minimizing the number of analog components and employing phase and frequency tracking loops for error correction, along with a decision-directed sample timing tracking loop for synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FSK/MSK I/Q receivers use two processing branches to recover complex-valued information, then signal recovery performance is improved, but power consumption increases due to more analog components
Solution Approach 1:
The patent extracts only the real part of the complex-valued information from the received signal by shifting it to the real axis through frequency offset mixing. This allows recovery of the complete bit information using a single channel instead of requiring both real and imaginary channels, thereby reducing the number of analog components and power consumption while maintaining signal recovery performance
Solution Approach 2:
The patent transforms the signal processing from a two-dimensional complex-valued domain to a one-dimensional real-valued domain by applying a frequency offset that shifts the complex information onto the real axis. This dimensional reduction enables single-channel operation and reduces the number of required analog components
2Use of energy by moving object
If smaller process technologies are used to reduce power consumption, then digital part power consumption decreases, but analog components still represent major power consumption that does not benefit from process technology scaling
Solution Approach 1:
The patent extracts and eliminates the need for one of the two processing branches by shifting complex information to the real axis, thereby removing half of the analog components (LNA, mixer, filter, ADC) from the system. This reduction in analog component count directly addresses the power consumption issue since analog components do not benefit from process technology scaling
3Use of energy by moving object
If a single channel approach is used to reduce power consumption, then number of analog components decreases, but phase and frequency errors may affect reception quality
Solution Approach 1:
The patent implements a phase tracking loop that continuously monitors the received signal and adjusts the frequency offset to compensate for phase and frequency errors. This feedback mechanism ensures that reception quality is maintained despite the simplified single-channel architecture and reduced number of analog components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The single channel approach significantly reduces power consumption while maintaining comparable sensitivity and adjacent channel rejection performance to traditional I/Q receivers, achieving efficient reception of frequency modulated signals in compliance with BLE 5.0 standards.
Implementation Method 1
mixing the received RF signal to a certain offset frequency
Data Source
Figure 1~2B
Figure 3A~3D
Figure 4
AI summary
A single channel receiver comprises an input terminal configured to receive an analog input signal, a mixer configured to down-mix the analog input signal by use of a phase- and/or frequency-corrected oscillator frequency signal and to shift complex-valued information contained in the analog input signal to the real part (or alternatively to the imaginary part) to obtain an intermediate real-valued analog signal, an analog-to-digital converter configured to convert the intermediate analog signal into an intermediate digital signal, a demodulator configured to demodulate the intermediate digital signal into a digital output signal, a phase tracking loop configured to detect zero-crossings in the intermediate digital signal to obtain phase error information representing a phase error in the intermediate digital signal, and an oscillator configured to generate the phase-and/or frequency-corrected oscillator frequency signal by compensating the phase and/or frequency error in the intermediate digital signal by correcting the phase of the oscillator frequency signal by use of the phase error information.