Single-Chip Memory Array Using Dual Chalcogenide Cell Types
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Solution Overview
Problem
Existing memory devices require separate chips for memory and storage, leading to increased costs, potential inoperability, reduced space, and complexity in computing systems.
Innovation Solution
A single chip incorporating both memory and storage capabilities using different chalcogenide material compositions for memory and storage cells, allowing for independent addressability via wordline and bitline selection, and formed through a series of etching and deposition steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate chips are used for memory and storage, then independent functionality is maintained, but device complexity and cost increase
Solution Approach 1:
The patent combines memory cells and storage cells into a single integrated device, allowing both functions to coexist on one chip. This merging reduces the number of separate components while maintaining the independent functionality of each cell type through distinct material compositions and operational mechanisms.
Solution Approach 2:
The integrated device performs multiple functions by incorporating both volatile memory capabilities and non-volatile storage capabilities in a single unit. The device can operate as memory when powered and as storage when unpowered, providing universal functionality that adapts to different operational states.
2Reliability
If separate chips are used for memory and storage, then functional independence is preserved, but space on printed circuit board increases
Solution Approach 1:
By merging memory and storage functions into a single integrated chip, the patent significantly reduces the total area required on the printed circuit board. The combined device replaces what would traditionally require two separate chips, thereby conserving valuable board space while maintaining functional independence through material-based differentiation.
3Reliability
If separate chips are used for memory and storage, then specialized functionality is maintained, but manufacturing cost increases
Solution Approach 1:
The patent reduces manufacturing costs by consolidating memory and storage fabrication into a single integrated process. While maintaining specialized functionality through different material compositions (chalcogenide for memory, oxide for storage), the combined device eliminates the need for separate chip procurement, packaging, and assembly operations.
Solution Approach 2:
The patent employs composite material structures where different materials (chalcogenide and oxide) are integrated within the same device architecture. This approach enables specialized functionality for each cell type while allowing both to be manufactured together in a single fabrication process, reducing overall manufacturing complexity and cost.
4Area of stationary object
If memory and storage are integrated on a single chip, then space is optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses distinctly different material compositions (chalcogenide vs. oxide) that can be deposited and differentiated through controlled manufacturing processes. The material differences provide clear process control points, allowing precise fabrication of both cell types simultaneously while maintaining optimized chip area through integration.
Data Source
AI summary
A single memory chip including both memory and storage capabilities on the single chip and accompanying process for forming a memory array including both capabilities is disclosed. In particular, the single chip may incorporate the use of two different chalcogenide materials deposited thereon to implement the memory and storage capabilities. Chalcogenide materials provide flexibility on cell performance, such as by changing the chalcogenide material composition. For the single memory chip, one type of chalcogenide material may be utilized to create memory cells and another type of chalcogenide material may be utilized to create storage cells. The process for forming the memory array includes forming first and second openings in a starting structure and performing a series of etching and deposition steps on the structure to form the memory and storage cells using the two different chalcogenide compositions. The memory and storage cells are independently addressable via wordline and bitline selection.