Single-chip Computer with Segmented Processor Cores for Secure Tachograph
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing vehicle computer systems lack a secure and efficient solution for separating safety-critical and non-safety-related functions, leading to complexities in certification and potential vulnerabilities.
Innovation Solution
A single-chip computer design featuring two processor cores with physical and logical separation, where one core handles non-security-related programs and the other executes cryptographic functions, with a shared interface for quick data exchange and internal peripheral units, enabling high security and performance while simplifying certification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processor cores are integrated on a single chip to improve performance and compactness, then device complexity and certification difficulty increase due to the need to certify entire multi-core systems
Solution Approach 1:
The chip is segmented into two independent processor cores: a first processor core for non-safety-related functions and a second processor core for safety-critical functions. Each core has its own program memory, data memory, and peripheral units, allowing them to operate independently with different security requirements. This segmentation enables separate certification of each core, reducing overall certification complexity while maintaining high processing performance.
2Reliability
If safety-critical and non-safety-related functions are executed on the same processor, then device compactness is improved, but security and reliability are compromised due to potential interference and certification complexities
Solution Approach 1:
Two independent processor cores with different security requirements are merged onto a single chip, sharing common resources such as the memory interface and peripheral units. This merging achieves physical compactness while maintaining logical separation through independent execution environments, ensuring both safety-critical and non-safety-related functions can coexist securely on the same chip without interference.
3Ease of operation
If external connections are used for data exchange between processor cores, then system flexibility is improved, but device compactness and performance are reduced due to additional external components and connection overhead
Solution Approach 1:
An intermediary communication mechanism is provided between the two processor cores, allowing efficient data exchange through a controlled interface on the same chip. This intermediary structure enables fast data transfer without requiring external connections, maintaining compactness while achieving high data exchange efficiency between the safety-critical and non-safety-related processing units.
Data Source
AI summary
A single-chip computer comprises at least one first processor core (P1) and at least one second processor core (P2), which are constructed on a common chip (C). The at least one first and the at least one second processor cores (P1, P2) are interconnected via a processor interface (PIF). Data can be read via a separate or common memory interface (MIF) from a separate or common data memory (DM) respectively and/or stored in said data memory. The single-chip computer additionally comprises an encryption and decryption unit (KRYPT) which is assigned to the at least one processor core (P2) and which is constructed and functionally arranged between the at least one second processor core (P2) and the memory interface (MIF) in such a way that the data which can be exchanged between the at least one second processor core (P2) and the data memory (DM) can be encrypted and decrypted by the encryption and decryption unit (KRYPT).