Single Chip Select Synchronous Serial Bus Interface
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Solution Overview
Problem
Conventional serial peripheral interfaces (SPI) require individual chip selects for each peripheral device, limiting the number of devices that can be accommodated and making the system prone to communication failures if one peripheral fails.
Innovation Solution
A synchronous serial bus interface that allows a host device to communicate with multiple peripheral devices using a single chip select, employing data frames with a command field, address field, and check field, and incorporating conflict detection to monitor bus activity and detect potential issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual chip selects are used for each peripheral device in conventional SPI, then communication reliability is improved, but the number of peripheral devices that can be accommodated is limited and hardware complexity increases
Solution Approach 1:
The patent combines multiple chip select functions into a single shared chip select signal by introducing address fields and device ID registers. Multiple peripheral devices share the same chip select line, and individual device selection is achieved through address decoding rather than separate chip select lines, thereby reducing hardware complexity while maintaining communication reliability
Solution Approach 2:
The single chip select signal serves multiple functions by addressing different peripheral devices through the address field in the data frame. This universal approach allows one chip select line to control multiple devices, eliminating the need for dedicated chip select lines for each device
2Ease of operation
If individual chip selects are used for each peripheral device, then device addressing is simplified, but the number of peripheral devices that can be accommodated is limited
Solution Approach 1:
The patent adds an address dimension to the communication protocol by introducing address fields in data frames and device ID registers. This allows devices to be selected through address decoding rather than through separate physical chip select lines, enabling exponential scaling of device capacity while maintaining simple addressing through the address field
3Device complexity
If a single chip select is used to communicate with multiple peripheral devices, then hardware requirements are reduced and device capacity increases, but communication reliability may worsen due to potential conflicts
Solution Approach 1:
The patent implements feedback mechanisms including acknowledgment frames and error detection codes (such as CRC) to ensure reliable communication. When a device receives data, it sends back an acknowledgment, and the host verifies data integrity using error detection, thereby maintaining communication reliability despite using a shared chip select line
Solution Approach 2:
The patent introduces protocol-level intermediaries including address fields, command fields, and control frames that mediate communication between the host and multiple devices. These intermediaries ensure that only the intended device responds to each transmission, preventing conflicts and maintaining reliability on the shared bus
4Reliability
If multiple peripheral devices are connected to a single chip select, then system reliability is enhanced through redundancy, but conflict detection becomes more difficult
Solution Approach 1:
The patent uses distinct address values (different 'colors' in the address space) to identify and differentiate between multiple peripheral devices. Each device has a unique address or ID that the host uses to selectively address specific devices, making conflict detection straightforward by verifying that the addressed device is the one responding
Solution Approach 2:
The patent employs feedback mechanisms where devices respond with acknowledgment frames containing their device IDs. The host can detect conflicts by verifying whether the responding device's ID matches the intended target, enabling easy conflict detection despite multiple devices sharing the same bus
Data Source
AI summary
A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.