Single-Circuit Multi-Bit Neuromorphic Processing by Time Division
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Solution Overview
Problem
Existing neuromorphic processors face inefficiencies in processing multi-bit operations due to limitations in handling multiple bits simultaneously, leading to suboptimal performance in neural network applications.
Innovation Solution
A neuromorphic apparatus with a single axon, synaptic, and neuron circuit, along with a controller, processes multi-bit operations in a time-division manner, sequentially assigning bits to these circuits to perform neuromorphic operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple circuits are used to process multi-bit operations simultaneously, then processing speed is improved, but hardware complexity and resource requirements increase
Solution Approach 1:
The patent applies periodic action by implementing time-division multiplexing where a single neuromorphic circuit processes multi-bit operations sequentially across different time periods. Each bit position (0th bit, 1st bit, etc.) is processed in a dedicated time slot, allowing the circuit to handle multi-bit operations efficiently without requiring multiple parallel circuits. This temporal segmentation resolves the contradiction by maintaining processing speed through systematic sequencing while minimizing hardware complexity.
Solution Approach 2:
The patent implements universality by designing a single neuromorphic circuit that can perform multiple functions - processing different bit positions of multi-bit operations at different time periods. The same circuit infrastructure handles 0th bit operations, 1st bit operations, and higher bit operations sequentially, making the hardware resource universal and multi-functional rather than requiring dedicated circuits for each bit position.
2Productivity
If multiple circuits are allocated for different bit positions, then processing capability is improved, but hardware resource requirements increase
Solution Approach 1:
The patent applies merging by combining multiple bit-position processing functions into a single neuromorphic circuit. Instead of allocating separate circuits for 0th bit, 1st bit, and other bit positions, the patent merges all these functions into one circuit that operates at different time periods. This consolidation maintains full processing capability for multi-bit operations while significantly reducing the quantity of hardware resources required.
Solution Approach 2:
The patent uses periodic action to enable a single circuit to handle multiple bit positions by assigning each bit position to a specific time period. The circuit processes the 0th bit in the first time period, the 1st bit in the second time period, and so on. This temporal organization allows the system to maintain high processing capability equivalent to having multiple circuits while using only one physical circuit.
3Device complexity
If a single circuit processes all bit positions sequentially, then hardware requirements are reduced, but processing time increases
Solution Approach 1:
The patent applies preliminary action by pre-assigning specific bit positions to specific time periods in a systematic manner. The controller is configured to determine which bit position (0th, 1st, 2nd, etc.) should be processed in each time period before execution. This preliminary organization of bit-position-to-time-period mapping allows the single circuit to process multi-bit operations efficiently without ad-hoc delays, minimizing processing time while maintaining reduced hardware requirements.
Data Source
AI summary
A neuromorphic apparatus configured to process a multi-bit neuromorphic operation including a single axon circuit, a single synaptic circuit, a single neuron circuit, and a controller. The single axon circuit is configured to receive, as a first input, an i-th bit of an n-bit axon. The single synaptic circuit is configured to store, as a second input, a j-th bit of an m-bit synaptic weight and output a synaptic operation value between the first input and the second input. The single neuron circuit is configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight, based on the output synaptic operation value. The controller is configured to respectively determine the i-th bit and the j-th bit to be sequentially assigned for each time period of different time periods to the single axon circuit and the single synaptic circuit.