Single-Clock AFE Sampling for Charge-Pump Noise Suppression
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Solution Overview
Problem
Conventional analog front-end (AFE) systems face significant noise suppression challenges due to charge-pump clock switching noise, particularly through ground bounce, which deteriorates the signal-to-noise ratio (SNR) despite aggressive ground and shield design strategies, and cost-driven PCB designs with single ground planes exacerbate this issue.
Innovation Solution
Implementing a single clock system that aligns the rising and falling edges of charge-pump clock signals with the ADC clock signals, allowing for efficient noise suppression by restricting sampling during charge-pump switching periods, thereby improving the SNR performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single ground plane is used in PCB design to reduce cost, then manufacturing cost is reduced, but noise coupling to sensitive sensor inputs deteriorates due to ground bounce
Solution Approach 1:
The patent merges the clock signal generation for the charge-pump and the sampler into a single clock domain. By using one common clock source and aligning their edges, the system reduces the number of separate clocking circuits and ground paths needed, allowing effective noise suppression even with a single ground plane.
Solution Approach 2:
The patent converts the potentially harmful charge-pump switching noise into a beneficial effect by deliberately synchronizing its clock edges with the sampler clock edges. This alignment causes the noise to occur predictably during periods when the sampler is not actively converting, thereby suppressing noise coupling to sensitive inputs while maintaining a simple single-ground-plane design.
2Object-affected harmful factors
If charge-pump rise/fall time is increased to reduce noise, then electromagnetic discharge is reduced, but productivity deteriorates due to slower clock switching
Solution Approach 1:
The patent employs periodic synchronization between the charge-pump clock and the sampler clock. By aligning the fast switching edges of both clocks to occur at specific periodic intervals when the sampler is inactive, the system maintains fast rise/fall times for high productivity while concentrating electromagnetic discharge noise into controlled periods that do not affect signal conversion.
3Adaptability or versatility
If separate clock sources are used for charge-pump and sampler, then operational flexibility is improved, but device complexity increases due to multiple clock signal lines
Solution Approach 1:
The patent combines multiple clock signal generation functions into a single clock source. By deriving both the charge-pump clock and the sampler clock from one common clock signal, the system reduces the number of clock signal lines and associated routing complexity while maintaining the ability to independently control the operation of each component through shared clock distribution.
Data Source
AI summary
An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal.