Single-Clock Encoder Modulation to Minimize Telemetry Phase Noise
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Solution Overview
Problem
Existing telemetry systems suffer from phase noise due to heterogeneous oscillators in FPGAs, leading to increased complexity and reduced design freedom, particularly in the modulation process.
Innovation Solution
Integrating encoder and transmission modulation functions into a single FPGA, utilizing a look-up table-based frequency pulse filter and quadrature modulator operated by a single clock, to minimize phase noise and reduce FPGA implementation complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encoder and modulation functions are implemented in separate FPGAs, then each module can be independently designed and maintained, but phase noise occurs due to heterogeneous oscillators and system complexity increases
Solution Approach 1:
The patent merges the encoder and modulation functions into a single integrated modulation unit within one FPGA. This consolidation eliminates the interface between separate FPGAs and their heterogeneous oscillators, thereby reducing phase noise while maintaining manageable system complexity through unified architecture design.
Solution Approach 2:
The integrated modulation unit performs multiple functions including encoding, modulation, and signal generation within a single FPGA device. This multi-functional approach reduces the number of separate components needed while improving signal quality by using a common oscillator source for all operations.
2Productivity
If multiple heterogeneous clocks are used in modulation units, then each component can operate at its optimal frequency, but clock domain crossing issues arise and design complexity increases
Solution Approach 1:
The patent uses a single homogeneous clock source for all operations within the modulation unit, including the encoder and modulator components. This eliminates clock domain crossing issues and simplifies timing synchronization while maintaining high message transfer rates through efficient single-clock architecture design.
3Manufacturing precision
If FIR filters with multiple multipliers are used, then filtering precision is improved, but FPGA implementation complexity increases and design freedom is reduced
Solution Approach 1:
The patent extracts the multiplication operations from the FIR filter implementation and replaces them with pre-computed lookup tables. This substitution maintains filtering precision by storing pre-calculated filter coefficients and output values, while significantly reducing the number of multipliers needed in the FPGA implementation.
Solution Approach 2:
The patent pre-computes and stores filter output values in lookup tables during the design phase. This preliminary action allows the runtime implementation to simply retrieve pre-calculated values through table lookup, eliminating the need for complex real-time multiplication operations and reducing FPGA resource requirements.
Data Source
AI summary
An encoder-integrated transmitter includes an encoder-integrated modulation unit including one field programmable gate array (FPGA) to control a measurement module, configured to collect measurement data from the measurement module to configure transmission frame data, and modulate the transmission frame data into a digital modulation signal and an amplification unit configured to convert the digital modulation signal into a passband analog radio frequency (RF) signal and then amplify the passband analog RF signal to a high power.