Single-Clock Dynamic Scannable Latch With Mode-Switched Feedback
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Solution Overview
Problem
Existing scannable latches in semiconductor circuits require multiple clock signals, leading to inefficiencies in power consumption and size, and are not useful in integrated circuits with a single clock, while also requiring precise transistor sizing for reliable data storage.
Innovation Solution
A dynamic scannable latch circuit that operates using a single clock for both functional and scan modes, incorporating a feedback keeper storage circuitry conditioned by a dynamic or static scan port, allowing reliable data storage and scanning without the need for multiple clocks or precise transistor sizing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock signals are used to implement scan function, then scanning capability is achieved, but power consumption increases and device size increases
Solution Approach 1:
The patent combines the functional mode and scan mode operations into a single clock signal system. The feedback keeper circuit is conditionally enabled based on the mode, allowing both scanning and normal operation to share the same clock infrastructure, thereby reducing power consumption and eliminating the need for separate clock signal paths.
Solution Approach 2:
The single clock signal serves dual purposes: it drives both the functional operation of the latch and the scan operation when the feedback keeper is disabled. This multi-functional use of the clock signal eliminates the need for separate clock signals for scanning, reducing overall power consumption and device complexity.
2Adaptability or versatility
If multiple clock signals are used to implement scan function, then scanning capability is achieved, but number of signal conductors increases
Solution Approach 1:
The patent merges the clock signal paths for functional mode and scan mode into a single shared path. By using one clock signal that conditionally drives both modes through the feedback keeper mechanism, the number of required signal conductors is reduced, thereby decreasing device area.
Solution Approach 2:
The single clock signal is designed to universally drive both functional and scan operations. This eliminates the need for separate dedicated clock conductors for scanning, reducing the total number of signal paths and the associated device area.
3Reliability
If transistor sizing is adjusted for reliable data storage, then data reliability improves, but device complexity increases
Solution Approach 1:
The patent employs a feedback keeper circuit that continuously monitors and maintains the stored data state. This feedback mechanism ensures reliable data storage without requiring complex transistor sizing ratios, as the feedback loop actively corrects and stabilizes the stored value, simplifying the design while maintaining high reliability.
4Device complexity
If single clock is used, then device complexity is reduced, but scan function cannot be implemented
Solution Approach 1:
The patent introduces dynamic control of the feedback keeper circuit based on the operational mode. During scan mode, the feedback keeper is disabled to allow scan data to pass through; during functional mode, it is enabled for data retention. This dynamic switching behavior allows a single clock to effectively perform both scan and functional operations, maintaining versatility while reducing complexity.
Data Source
AI summary
A latch has a first mode in which the latch functions as a dynamic latch and a second mode in which the latch functions as a static latch. The latch has a feedback circuit that in turn has two parallel switchable loads. The first load is responsive to a data input signal of the latch in the first mode and disabled in the second mode. The second load is responsive to a clock signal in the second mode and disabled in the first mode. The switchable loads being in parallel provides for the ability to select the feedback that is better for the particular mode of operation. The first and second switchable loads can be optimized for the particular mode of operation that will use it.