Single-Clock Insertion Sort Circuit for Real-Time Data

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Solution Overview

Problem

Existing insertion sorting algorithms are time-consuming when executed in software, particularly for real-time sorting of sequential data streams, due to the need for numerous compare operations.

Innovation Solution

A single-clock cycle sorting circuit with a low gate count and minimal combinatorial delays, utilizing a stack of stages with comparators and multiplexers to sort input data values based on their magnitude within a single clock cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If insertion sorting is performed by executing instructions on a processor in software, then the sorting can be implemented with flexible control, but the sorting process becomes relatively time-consuming due to the requirement of performing numerous compare operations

Engineering Contradiction:

Improveimplementation flexibilityVSAvoidsorting execution time

Core Design Contradiction:

Ease of operationVSLoss of time

Solution Approach 1:

The patent replaces the software-based mechanical instruction execution system with a hardware-based digital circuit system. The sorting logic is implemented using comparators, multiplexers, and registers that physically compare and sort data values in parallel, eliminating the sequential nature of software execution and dramatically reducing sorting time.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The sorting circuit is divided into multiple stages, with each stage containing comparators and multiplexers that handle specific comparison and selection tasks. This segmentation allows the sorting process to be broken down into parallel operations across different stages, improving overall sorting speed while maintaining implementation flexibility.

Inventive Principle:

Principle #1Segmentation

2Productivity

If a high-speed hardware architecture is designed to perform insertion sorting in real time, then the sorting speed increases, but the gate count and power requirements increase

Engineering Contradiction:

Improvesorting speedVSAvoidgate count

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The circuit uses dynamic control signals to enable only the necessary comparators and multiplexers for each sorting operation. This dynamic activation reduces the effective gate count during operation, as not all hardware components need to be active simultaneously, thereby lowering power consumption while maintaining high sorting speed.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The circuit performs preliminary comparisons and selections in parallel across multiple stages before finalizing the sorted output. This preliminary action allows the sorting to be completed in fewer clock cycles, improving productivity without requiring a proportional increase in gate count.

Inventive Principle:

Principle #10Preliminary action

3Productivity

If a high-speed hardware architecture is designed to perform insertion sorting in real time, then the sorting speed increases, but the power requirements increase

Engineering Contradiction:

Improvesorting speedVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The circuit employs dynamic power management by enabling only the necessary comparators and multiplexers for each sorting operation. This dynamic activation reduces the effective gate count during operation, thereby lowering power consumption while maintaining high sorting speed.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The sorting circuit operates in periodic clock cycles, with each cycle performing a specific stage of the sorting process. This periodic operation allows the circuit to reset and reconfigure between cycles, reducing average power consumption compared to continuous operation, while still achieving real-time sorting throughput.

Inventive Principle:

Principle #19Periodic action

4Speed

If a hardware architecture with minimal combinatorial delays is designed, then the clock rate can be increased, but the circuit design becomes more constrained

Engineering Contradiction:

Improveclock rateVSAvoidcircuit design flexibility

Core Design Contradiction:

SpeedVSEase of manufacture

Solution Approach 1:

The circuit is segmented into multiple stages, each with controlled combinatorial logic depth. By dividing the sorting logic into discrete stages with registers between them, the maximum combinatorial delay in any single stage is limited, allowing for higher clock rates while maintaining reasonable design flexibility within each stage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12210371B2Single-clock insertion sort scheme

Publication Date: 2025.01.28 L3HARRIS TECH INC

AI summary

A sorting circuit includes: a stack of registers for storing a set of data values from a highest value to a lowest value; a set of comparators for substantially simultaneously comparing an input data value to the set of data values stored in the registers, where the comparators enable registers whose stored data values are less than the input data values to receive a replacement data value; and a set of multiplexers, each associated with a register in the stack to select the replacement data value when the register is enabled. The multiplexer selects the input data value to be the replacement data value if the register is the highest register in the stack currently storing a data value that is less than the input data value. Otherwise, the multiplexer selects the data value stored in the next-highest register in the stack to be the replacement data value.