Single Comparator Circuit for Memory Signal Multiplexing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuit memory devices, multiple comparators consume significant constant current and occupy substantial space, hindering efficiency and cost-effectiveness when comparing multiple test signals to reference signals.
Innovation Solution
Implementing a single comparator circuit that serially compares each test signal to a single reference signal or multiple reference signals, reducing DC current draw and occupied area by using a multiplexer and latch system to manage signal selection and comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple comparators are used to compare multiple test signals to reference signals, then comparison functionality is improved, but DC current draw increases and area occupied increases
Solution Approach 1:
The patent combines multiple comparator functions into a single comparator by using a multiplexer to sequentially connect different test signals to the same comparator. This merging approach maintains the ability to compare multiple test signals while using only one comparator, thereby reducing DC current draw and occupied area.
Solution Approach 2:
The patent implements periodic action by sequentially comparing test signals over time using a single comparator. The multiplexer switches between different test signals in a periodic manner, allowing one comparator to perform the work of multiple comparators over time, thus reducing power consumption and area while maintaining comparison functionality.
2Adaptability or versatility
If multiple comparators are used to compare multiple test signals to reference signals, then comparison functionality is improved, but area occupied increases
Solution Approach 1:
The patent merges multiple comparator circuits into a single comparator circuit by using a multiplexer to route different test signals to the same comparator at different times. This consolidation reduces the total area occupied while maintaining the capability to compare multiple test signals through sequential operation.
Solution Approach 2:
The patent transitions from a spatial arrangement (multiple comparators side by side) to a temporal arrangement (single comparator operating sequentially). By adding the time dimension to the comparison process, the system achieves the same functionality with reduced area occupation.
3Use of energy by moving object
If a single comparator is used to serially compare test signals, then DC current draw is reduced and area occupied is reduced, but comparison speed may be reduced
Solution Approach 1:
The patent uses periodic action by sequentially switching between different test signals using a multiplexer. The single comparator operates continuously at full speed, comparing each signal in turn, which maintains high comparison speed while using less power than multiple parallel comparators would require.
Solution Approach 2:
The patent introduces dynamic signal routing through the multiplexer, which actively switches between different test signals based on timing control. This dynamic approach allows the single comparator to efficiently process multiple signals in sequence, maintaining high speed while reducing power consumption.
Data Source
AI summary
A device includes a comparator, a reference signal node, a plurality of test signal nodes, and control logic. The reference signal node receives a reference signal. The reference signal node is coupled to a first input of the comparator. Each of the plurality of test signal nodes receives a corresponding test signal. The control logic is configured to initiate a comparison of each test signal to the reference signal via the comparator.