Single-Conductivity Amplifier Buffer With Boosted Rail-to-Rail Output
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Solution Overview
Problem
Existing single conductivity type amplifier/buffers face challenges with high power dissipation and limited rail-to-rail output range, which restricts cascading and increases manufacturing costs due to complex lithographic processes and suboptimal transistor configurations.
Innovation Solution
A single threshold and single conductivity type amplifier/buffer circuit incorporating a boosting circuit with an energy storage facility and identification circuit to enhance output swing, utilizing either P-conductivity or N-conductivity type elements, reduces manufacturing costs and power dissipation by enabling rail-to-rail output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single conductivity type amplifier/buffer is used to reduce manufacturing costs, then manufacturing complexity is reduced, but power dissipation increases significantly
Solution Approach 1:
The patent implements dynamic operation by using complementary clock signals (CLKA, CLKB) to alternately activate different transistor pairs. The circuit switches between N-type and P-type transistor conduction based on clock phases, enabling rail-to-rail output swing while maintaining low static power consumption through dynamic switching control.
Solution Approach 2:
The circuit employs periodic clock signals to alternately drive N-type and P-type transistor pairs. During one clock phase, N-type transistors conduct while P-type transistors are off, and vice versa during the opposite phase. This periodic switching enables full output swing without continuous current draw, resolving the power dissipation issue.
2Ease of manufacture
If diode-connected transistors are used to achieve single threshold logic, then output voltage range is limited to Vdd-VT, but manufacturing simplicity is improved
Solution Approach 1:
The circuit uses dynamic switching between different transistor configurations controlled by complementary clock signals. During different clock phases, different transistor pairs are activated, allowing the output to reach both Vdd and GND levels dynamically, achieving rail-to-rail output without being limited by static diode-connected transistor thresholds.
Solution Approach 2:
The circuit changes its operational parameters dynamically by switching between different transistor pairs with different conductivity types. By alternating between N-type and P-type transistor conduction based on clock phases, the circuit achieves full output voltage swing while maintaining single-threshold transistor fabrication.
3Ease of operation
If complementary CMOS circuits are used to achieve rail-to-rail output, then output impedance is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent uses a unified circuit architecture that performs multiple functions: buffering, amplification, and rail-to-rail output generation, all using single-threshold transistors of a single conductivity type. The complementary clocking scheme enables the same transistor type to function in both pull-up and pull-down roles at different times, eliminating the need for separate P-type and N-type transistor fabrication processes.
Solution Approach 2:
The circuit achieves CMOS-like functionality by dynamically changing the conductivity type of active transistors through clock-controlled switching. During different clock phases, either N-type or P-type transistors are activated, effectively creating time-multiplexed complementary operation using only single-threshold transistor fabrication.
Data Source
AI summary
An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.