Single-Conductivity Non-Planar ICs for Low-Temperature Computing
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Solution Overview
Problem
Existing CMOS integrated circuits face challenges in fabrication complexity and limitations, necessitating improved computational devices for efficient computation with reduced times and increased performance, particularly in low temperature environments.
Innovation Solution
Deployment of single conductivity type non-planar transistors, such as Fin FETs, GAA FETs, and nanosheet FETs, in integrated circuits, combined with active cooling structures to maintain operating temperatures at or below 0°C, utilizing back-side power delivery for enhanced carrier mobility and reduced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CMOS devices are deployed with both n-type and p-type transistors, then functional versatility is improved, but fabrication complexity increases
Solution Approach 1:
The patent extracts one conductivity type from the traditional CMOS dual-type configuration, implementing only n-type MOS transistors in the integrated circuit. This removal of p-type transistors simplifies fabrication processes while maintaining computational functionality through alternative circuit design approaches.
Solution Approach 2:
The patent changes the operational parameters by operating the single-conductivity-type circuit at reduced temperatures (below 0°C to -100°C). This temperature parameter change enables n-type-only circuits to achieve performance comparable to or exceeding traditional CMOS, resolving the trade-off between simplicity and functionality.
2Ease of manufacture
If traditional planar transistors are used, then manufacturing simplicity is maintained, but performance at low temperature deteriorates
Solution Approach 1:
The patent transitions from planar (flat) transistor structures to non-planar configurations such as FinFETs with vertical fins or nanosheet structures. These curved/three-dimensional geometries provide superior electrical control and carrier mobility at low temperatures while remaining compatible with standard semiconductor fabrication processes.
Solution Approach 2:
The patent moves transistor architecture from two-dimensional planar structures to three-dimensional non-planar structures. This dimensional transition enables improved performance at low temperatures by enhancing the electric field control and reducing short-channel effects, while the fabrication processes remain relatively straightforward.
3Reliability
If high temperature operation is maintained, then device reliability is improved, but computational efficiency deteriorates
Solution Approach 1:
The patent inverts the conventional approach by changing the temperature parameter from high to low (below 0°C). This parameter change simultaneously improves computational efficiency through reduced thermal noise and leakage currents while maintaining device reliability through the use of non-planar transistor structures that perform well at low temperatures.
Solution Approach 2:
The patent substitutes thermal management approaches by replacing active cooling requirements with passive low-temperature operation. The non-planar transistor structures inherently benefit from low temperature operation, eliminating the need for complex thermal control systems while improving computational efficiency.
4Ease of manufacture
If standard CMOS fabrication processes are used, then manufacturing simplicity is maintained, but device performance at reduced temperature deteriorates
Solution Approach 1:
The patent employs non-planar transistor structures such as FinFETs and nanosheet devices that can be fabricated using modified standard CMOS processes. These curved/three-dimensional structures provide superior low-temperature performance while remaining compatible with existing semiconductor manufacturing capabilities.
Solution Approach 2:
The patent transitions from two-dimensional planar transistors to three-dimensional non-planar structures, enabling improved low-temperature performance through enhanced electrical control. The fabrication processes for these structures have been integrated into standard CMOS manufacturing flows, maintaining ease of manufacture while achieving superior device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Non-planar single MOS transistors exhibit increased performance with reduced contact resistance and leakage, achieving improved computational efficiency and reduced IR drop in low temperature environments.
Implementation Method 1
a cooling structure operable to remove heat from the IC die to achieve an operating temperature at or below 0°C
Data Source
AI summary
Integrated circuit dies, systems, and techniques, are described herein related to single conductivity type transistor circuits operable at low temperatures. A system includes a functional circuit block of an integrated circuit die having a number of non-planar transistors all of the same conductivity type. The system further includes cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve an operating temperature at the desired low temperature.