Single-Conductor Non-Volatile Memory Cell Erasing Structure
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Solution Overview
Problem
Conventional non-volatile memory cells require high-voltage wells and additional fabrication steps due to high erasing voltages, which are not compatible with standard CMOS processes.
Innovation Solution
A single-conductor non-volatile memory cell design featuring an isolation layer, a storage transistor with a first well and a floating gate, and an erasing transistor with a second well and a second segment of the floating gate, allowing for erasure using lower voltages without the need for high-voltage wells, utilizing either Fowler-Nordheim tunneling or band-to-band tunneling hot hole injection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage wells (HV P-well or deep N-well) are used for erasing conventional non-volatile memory cells, then erasing function is achieved, but device complexity and fabrication process complexity increase due to extra forming steps not included in standard CMOS process
Solution Approach 1:
The floating gate is divided into two separate segments: a first segment positioned over the first well for storage transistor operation, and a second segment positioned over the second well for erasing transistor operation. This segmentation allows each well to be optimized for its specific function without requiring high-voltage structures throughout the entire device.
Solution Approach 2:
The isolation layer serves as an intermediary structure that electrically isolates the first well from the second well. This isolation enables the second well to achieve the necessary voltage potential for erasing through the erasing transistor without requiring high-voltage wells, as the isolation layer prevents voltage interference from the storage transistor region.
2Reliability
If high-voltage wells are used for erasing, then erasing function is achieved, but manufacturing complexity increases due to extra fabricating steps combined with standard CMOS process
Solution Approach 1:
The standard CMOS fabrication process is made universal by designing both the storage transistor and erasing transistor to use the same well structures (first well and second well respectively) that can be formed using standard CMOS techniques. The floating gate structure serves dual purposes: enabling storage transistor writing/reading through the first well and enabling erasing through the second well, all within the standard CMOS process framework.
3Reliability
If conventional stacked gate structure with floating gate and control gate is used, then non-volatile memory function is achieved, but device complexity increases due to extra gate layers requiring additional fabricating steps
Solution Approach 1:
The storage transistor and erasing transistor are merged into a single device structure sharing common elements: the same substrate, the same floating gate (with two segments), and adjacent well structures. This merging eliminates the need for separate control gates and reduces the overall device complexity while maintaining both storage and erasing functions.
Solution Approach 2:
The floating gate structure performs multiple functions: it serves as the charge storage element for the storage transistor and simultaneously serves as the control electrode for the erasing transistor. This multi-functionality eliminates the need for separate control gates that would be required in conventional stacked gate structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables erasure at lower voltages without the requirement for high-voltage wells, simplifying the fabrication process and integrating seamlessly with standard CMOS processes.
Implementation Method 1
In a writing process of such a storage transistor, hot electrons are drawn into the floating gate due to a positive potential thereof induced by a positive voltage applied to the S/D region overlapping with the floating gate
Implementation Method 2
In a channel FN erasing method, as shown in FIG. 1, a quite high voltage about 20V is applied to the substrate and the S/D regions grounded, so that electrons are ejected out of the floating gate 100 through FN tunneling
Implementation Method 3
In an edge FN erasing method, as shown in FIG. 2, a high voltage about 12V is applied to the source region to draw the electrons from the floating gate 200
Data Source
AI summary
A storage unit of a single-conductor non-volatile memory cell is described, which includes an isolation layer in a substrate, a storage transistor and an erasing transistor. The storage transistor includes a first well of a first conductivity type in the substrate beside the isolation layer, a floating gate crossing over the isolation layer and including a first segment over the first well, and two source/drain regions of a second conductivity type in the first well beside the first segment of the floating gate. The erasing transistor includes a second well of the first conductivity type located in the substrate and separated from the first well by the isolation layer, a second segment of the floating gate over the second well, and a well pickup region of the first conductivity type in the second well beside the second segment of the floating gate.