Single Control Gate 3D NAND Flash Memory Cell
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Solution Overview
Problem
Conventional three-dimensional NAND flash memory devices with floating gate memory cells face issues of deteriorated data retention characteristics and lower erase speed compared to two-dimensional floating-gate memory cells, and have complex operating conditions due to the need for multiple control gates to drive each memory cell.
Innovation Solution
A semiconductor device with a single control gate coupled to each floating gate memory cell, where the floating gate is embedded within the control gate, reducing the number of control gates required and simplifying operating conditions, and enhancing the coupling ratio between the control gate and floating gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple control gates are stacked to drive each memory cell in conventional three-dimensional NAND flash, then the memory cell can be operated, but the device complexity and operating conditions become complex
Solution Approach 1:
The patent extracts and removes the unnecessary control gates from the conventional multi-control gate structure. By using a single control gate instead of multiple stacked control gates, the patent simplifies the operating conditions and reduces device complexity while maintaining the functionality of the memory cell
Solution Approach 2:
The patent merges the functionality of multiple control gates into a single control gate. The single control gate is designed to control multiple floating gates simultaneously, combining the operations that previously required separate control gates into one unified control structure
2Area of stationary object
If conventional three-dimensional structure is used with multiple control gates, then memory cells can be formed, but the size of the semiconductor device increases
Solution Approach 1:
The patent removes the stacked control gate structure from the conventional design. By extracting the unnecessary control gates and interlayer insulating layers, the patent reduces the vertical height and overall device size while maintaining the three-dimensional memory cell functionality
Solution Approach 2:
The patent reconfigures the memory cell structure to achieve three-dimensional integration without requiring multiple stacked control gates. The single control gate controls floating gates arranged in a different spatial configuration, achieving vertical integration through alternative dimensional arrangement
3Reliability
If floating gate is not embedded within control gate, then manufacturing is simpler, but the coupling ratio between control gate and floating gate is reduced
Solution Approach 1:
The patent implements a nested structure where the floating gate is embedded within the control gate. The floating gate is positioned inside the control gate structure, creating a nested configuration that enhances the coupling ratio between the control gate and floating gate while maintaining manufacturability
Data Source
AI summary
A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates.