Single-Controller MRI Control With Dynamic Command Scheduling
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Solution Overview
Problem
Conventional MRI systems require a large bank of controllers to manage precise timing of commands to MRI components, leading to inefficiencies in bandwidth and memory usage, especially when using a single controller with relaxed timing requirements.
Innovation Solution
A single controller, such as an FPGA, is used to dynamically issue commands to MRI components while receiving further commands, with techniques involving command prioritization and waveform compression to reduce the number of commands needed, allowing for efficient operation with relaxed timing constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large bank of controllers is used to manage precise timing of commands to MRI components, then timing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the functions of multiple controllers into a single controller that can dynamically manage command issuance to MRI components. This single controller consolidates the timing control, command prioritization, and waveform generation functions that previously required multiple separate controllers, thereby reducing device complexity while maintaining timing precision through software-based scheduling and prioritization mechanisms.
2Device complexity
If a single controller is used to control MRI components, then device complexity is reduced, but timing precision deteriorates
Solution Approach 1:
The patent implements dynamic command prioritization and scheduling within the single controller to adaptively manage timing requirements. The controller dynamically adjusts the priority and issuance timing of commands based on real-time system state and timing constraints, ensuring that critical timing requirements are met even with a single controller. This dynamic approach allows the system to maintain timing precision without requiring multiple static controllers.
Solution Approach 2:
The patent employs preliminary waveform compression and command buffering to prepare control signals in advance. By pre-processing and compressing waveforms before issuance, the single controller can efficiently manage timing-critical commands without real-time processing delays. This preliminary action ensures that timing precision is maintained while using a simplified single-controller architecture.
3Reliability
If command sequences are fully received before issuance, then control reliability is improved, but productivity and efficiency deteriorate
Solution Approach 1:
The patent implements a streaming command issuance mechanism where commands are received and issued in a continuous flow rather than waiting for complete sequences. The single controller can begin issuing commands as they are received from the processor, while simultaneously receiving subsequent commands. This preliminary action approach maintains reliability through buffer management and error checking while significantly improving productivity by eliminating the waiting period for complete command sequence reception.
Solution Approach 2:
The patent enables continuous operation of the MRI system by allowing the controller to continuously receive and issue commands without interruption or idle waiting periods. The controller maintains a continuous stream of command processing, where reception and issuance operations overlap in time. This continuity eliminates gaps in the control signal flow, maintaining system reliability while maximizing productivity through uninterrupted operation.
Data Source
AI summary
Techniques are described for controlling components of a Magnetic Resonance Imaging (MRI) system with a single controller, such as a Field Programmable Gate Array (FPGA), by dynamically instructing the controller to issue commands to the components using a processor coupled to the controller. According to some aspects, the controller may issue commands to the components of the MRI system whilst actively receiving commands from the processor to be later issued to the components.