Single Core Packet Classification for Control and Data Plane Separation

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Solution Overview

Problem

Conventional packet processing systems require separate central processing units (CPUs) for control plane and data plane operations, leading to increased costs and complexity, and limited scalability and flexibility.

Innovation Solution

Implementing a single processing core with distinct threads to perform both control plane and data plane operations, using a packet classifier to differentiate between known and unknown packet flows, and employing fast interrupt requests and Just-in-time rule compilation to process packets efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate CPUs are used for control plane and data plane operations, then reliability and functional separation are improved, but device complexity and cost increase

Engineering Contradiction:

Improvefunctional separationVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges control plane and data plane operations into a single processing core, eliminating the need for separate CPUs. The single core dynamically switches between handling control plane packets (CCP) and data plane packets (CDP) based on packet classification, thereby reducing device complexity and cost while maintaining functional separation through software-based isolation.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The single processing core is designed to perform multiple functions by implementing both control plane and data plane operation handlers. The core can act as a control plane processor when CCP is received and as a data plane processor when CDP is received, achieving multi-functionality without requiring separate dedicated processors for each plane.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If separate CPUs are used for control plane and data plane operations, then operational independence is improved, but ease of operation and scalability worsen

Engineering Contradiction:

Improveoperational independenceVSAvoidease of operation

Core Design Contradiction:

Adaptability or versatilityVSEase of operation

Solution Approach 1:

The system implements dynamic operation modes where the processing core can switch between control plane and data plane handling based on real-time packet classification. This dynamic adaptability allows the system to maintain operational independence when needed while simplifying operation during normal data flow, improving both adaptability and ease of operation.

Inventive Principle:

Principle #15Dynamics

3Device complexity

If a single processing core is used for both control plane and data plane operations, then device complexity and cost are reduced, but processing performance may deteriorate

Engineering Contradiction:

Improvedevice complexityVSAvoidprocessing performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent segments packet processing into two distinct paths: control plane packet handling and data plane packet handling. By classifying packets at the beginning and routing them through appropriate processing threads, the system avoids context switching overhead and ensures that each type of packet is processed efficiently by dedicated logic, thereby maintaining high processing performance despite using a single core.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system performs preliminary packet classification at the start of processing to determine whether a packet belongs to the control plane or data plane. This preliminary action enables the system to immediately route the packet through the appropriate processing path without subsequent context switching or re-evaluation, maximizing processing efficiency.

Inventive Principle:

Principle #10Preliminary action

4Device complexity

If a single processing core is used for both control plane and data plane operations, then cost is reduced, but network performance may be limited

Engineering Contradiction:

ImprovecostVSAvoidnetwork performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent changes the operational parameters of the single processing core by implementing context-aware processing modes. The core adjusts its behavior based on the packet type being processed, optimizing instruction execution paths and resource allocation dynamically. This parameter adaptation allows the single core to achieve network performance comparable to or exceeding that of multi-CPU systems while maintaining lower cost.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9130776B2Data path acceleration using HW virtualization

Publication Date: 2015.09.08 MARVELL ASIA PTE LTD

AI summary

A processing core includes a packet classifier, implemented in a single processing core, configured to classify incoming data packets into first data packets of a known data packet flow and into second data packets of an unknown data packet flow, a first path thread, implemented in the single processing core, configured to process ones of the first data packets at least by forwarding the first data packets to a destination that corresponds to a previously determined destination associated with the known data packet flow, and a second path thread, implemented in the single processing core, configured to process a received second data packet at least to determine a new data packet flow for the second data packet.