Single-Core Temporal Lockstep for Processor Error Detection

The processor is segmented into two functional phases: a dummy phase for error detection and a real phase for actual computation. The dummy phase executes identical instructions to the real phase but discards results, while the real phase executes instructions and commits results. This temporal segmentation allows error detection without requiring additional processor cores, resolving the contradiction between reliability and device complexity.

The processor alternates between dummy phase execution and real phase execution in a periodic manner. For each instruction, the dummy phase executes first to detect potential errors, followed by the real phase execution to perform actual computation. This periodic alternation enables continuous error detection while maintaining single-core operation, addressing the contradiction between error detection capability and processor core quantity.

The computation process is segmented into dummy phase execution (for error detection) and real phase execution (for actual work). The dummy phase consumes power for instruction decoding and execution but discards results, while the real phase consumes power for both execution and result commitment. This segmentation enables error detection using the same processor core, avoiding the additional power consumption that would result from running duplicate processor cores.

The processor serves its own error detection needs by using its own execution resources during the dummy phase. The same processor core that will execute the real instruction also executes the dummy instruction for error detection purposes. This self-service approach eliminates the need for separate error detection hardware, thereby reducing overall power consumption while maintaining error detection capability.

The processor periodically alternates between dummy phase execution and real phase execution for each instruction. The dummy phase executes the instruction to detect errors, and the real phase executes the same instruction to produce actual results. This periodic alternation within a single core enables error detection without the time penalty of parallel execution on multiple cores, as the same hardware resources are reused sequentially.

The error detection function and the computation function are merged into a single processor core through temporal multiplexing. The dummy phase performs error detection by executing instructions, and the real phase performs computation by executing the same instructions. By merging these functions into one core rather than using separate cores, the system achieves error detection capability while minimizing processing time overhead.

The processor functionality is segmented into dummy phase execution units and real phase execution units that share the same physical hardware resources. The instruction decoder, execution units, and registers are reused between dummy and real phases rather than being duplicated. This segmentation approach enables error detection capability while maintaining a compact single-core architecture, resolving the contradiction between reliability and processor area.

The processor core is designed with universal functionality that serves both error detection and computation purposes. The same execution units, registers, and control logic are used during both the dummy phase (for error detection) and the real phase (for computation). This multi-functionality eliminates the need for dedicated error detection hardware, thereby reducing the overall processor area while maintaining robust error detection capability.