Single-Counter ADC Circuit for Low-Area Crosstalk-Free Conversion
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) in image sensors require two counters per pixel column, leading to large area usage and potential crosstalk due to shared power supplies, while also consuming constant power and having reduced clock frequency.
Innovation Solution
A single counter circuit is used in the ADC, capable of both up-and down-counting dynamically without stopping the input clock, ensuring signal-independent power consumption and avoiding crosstalk through shared supply and ground nets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If two counters per pixel column are used to achieve reduced clock frequency and constant power consumption, then power consumption is reduced and clock frequency is lowered, but area per ADC increases
Solution Approach 1:
The patent merges two separate counters (up-counter and down-counter) into a single counter that can dynamically switch between up-counting and down-counting modes. This single counter is controlled by a control stage that receives comparator output signals and configures the counter accordingly, eliminating the need for two separate counter circuits and reducing the area per ADC while maintaining constant power consumption and reduced clock frequency benefits
2Area of stationary object
If a single counter is used to reduce area, then area per ADC is reduced, but power supply control becomes difficult leading to crosstalk between parallel ADCs
Solution Approach 1:
The patent implements a dynamic counter configuration where a control stage actively manages the counter's operating mode (up-counting or down-counting) based on comparator output signals. This dynamic control ensures that the single counter operates in a signal-independent manner, maintaining constant power consumption regardless of the converted signal level, thereby preventing crosstalk between parallel ADCs while keeping the area per ADC small
3Measurement precision
If two counters with adder are used, then conversion accuracy is maintained, but device complexity increases
Solution Approach 1:
The patent creates a universal counter circuit that can perform both up-counting and down-counting functions depending on the configuration signal from the control stage. This multi-functional counter replaces the need for separate up-counter, down-counter, and adder circuits, reducing device complexity while maintaining conversion accuracy through dynamic mode switching based on comparator output signals
Data Source
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AI summary
An analog-to-digital converter (300), ADC, for enabling a calculation of a difference between a first analog signal level (Vsig) and a second analog signal level (Vres), the ADC (300) comprising: at least one input (311) for receiving an input signal, comprising one of the first analog signal level (Vsig) and the second analog signal level (Vres); an input (310) for receiving a ramp signal (Vramp); an input (313) for receiving an input clock (CLK); a counter (303), configurable to count in a counting direction being either of a first counting direction and a second counting direction; a comparator (301), configured to generate a comparator output signal based on a comparison of the ramp signal (Vramp) with the input signal; and a control stage, configured to enable the counter (303) to count in the first counting direction based on the comparator output signal, and to enable the counter (303) to count in the second counting direction based on an inversion of the comparator output signal.