Single-Counter Frequency Lock Detection for Asynchronous Clocks
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Solution Overview
Problem
Conventional frequency lock detectors using two counters face increased complexity and power consumption as desired frequency accuracy increases, making it difficult to integrate them effectively.
Innovation Solution
A frequency lock detector using one counter and a clock number difference detector to compare the frequencies of two clock signals without phase synchronization, determining frequency lock based on the difference between the counted clock numbers, which maintains low complexity regardless of the desired frequency accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If two counters are used to compare frequencies with high accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of two separate counters into a single counter that sequentially counts clock cycles of both the reference clock signal and the recovered clock signal. This single counter approach maintains the ability to compare frequencies with high accuracy while significantly reducing the hardware complexity and resource requirements compared to using two independent counters with large counting capacities.
Solution Approach 2:
The patent segments the counting process into two distinct phases: first counting the reference clock signal cycles, then counting the recovered clock signal cycles within the same counter resource. This temporal segmentation allows one counter to perform the work of two counters, reducing device complexity while maintaining measurement precision for frequency comparison.
2Measurement precision
If two counters with large counting capacity are used, then frequency accuracy is improved, but power consumption increases
Solution Approach 1:
The patent combines the counting operations of two large-capacity counters into a single counter that alternates between counting reference clock cycles and recovered clock cycles. This merging reduces the total power consumption because only one counter is actively counting at any given time, halving the dynamic power requirements while maintaining the same frequency comparison accuracy.
Solution Approach 2:
The patent implements periodic action by alternating the counter's counting target between reference clock signals and recovered clock signals in sequential time periods. This periodic switching allows the system to maintain high frequency measurement accuracy through adequate sampling while reducing instantaneous and average power consumption compared to having two counters operating simultaneously at full capacity.
3Measurement precision
If two counters are used for frequency comparison, then measurement precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent merges two counter units into a single integrated counter module that can be implemented with fewer logic elements and smaller area on an integrated circuit. This consolidation simplifies the manufacturing process, reduces design complexity, and improves ease of integration into clock data recovery circuits while maintaining the precision needed for frequency lock detection.
Solution Approach 2:
The patent creates a universal counter that can count different clock signals (reference or recovered) based on control signals, making it a multi-functional unit. This universal counter design is easier to manufacture and integrate than two specialized counters, as it uses the same hardware resources for multiple counting purposes, reducing overall circuit complexity and improving manufacturability.
Data Source
AI summary
Provided is a frequency lock detector which includes one counter and a clock number difference detector for detecting a clock number difference while not increasing complexity according to the counting number N to compare the frequencies of two clock signals whose phases are not synchronous to each other and determine whether the difference between the frequencies of the two signals is within a desired frequency accuracy. The frequency lock detector includes: a counter for counting the number of clocks of a reference clock signal inputted from outside; a clock number difference detector for detecting a difference between the clock number of the reference clock signal and the clock number of a recovered clock signal whose phase is not synchronous to the phase of the reference clock signal; and a lock determiner for determining a frequency lock based on result values of the counter and the clock number difference detector.