Single CPU Power Management via Dynamic Voltage and Frequency Scaling
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Solution Overview
Problem
Existing processor systems require separate CPUs and buses for high performance and low power modes, leading to increased code complexity, storage requirements, and inefficient power consumption, as they lack a single CPU and executable code image capable of discrete performance and power adjustments.
Innovation Solution
A System on a Chip (SoC) architecture with a single CPU operating at multiple voltages and clock rates, coupled to high speed and low power buses, featuring a performance register that enables incremental performance levels, clock sources, and power distribution, allowing for seamless transitions between modes while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If separate CPUs are used for high performance and low power modes, then performance and power consumption are optimized for specific tasks, but device complexity and code storage requirements increase
Solution Approach 1:
The patent merges the functionality of multiple CPUs into a single CPU that can dynamically adjust its performance characteristics. The single CPU implements both high-performance and low-power modes through voltage and frequency scaling, eliminating the need for separate processor units while maintaining the ability to optimize for different power requirements.
Solution Approach 2:
The single CPU is designed to be universal, capable of operating in multiple performance modes (high-performance and low-power) depending on system requirements. This multi-functionality is achieved through dynamic voltage and frequency adjustment, allowing the same processor to serve different computational needs without requiring separate specialized units.
2Use of energy by moving object
If separate CPUs with different instruction sets are used, then performance and power consumption are optimized, but code storage requirements and development complexity increase
Solution Approach 1:
The single CPU implements a universal instruction set that can execute the same code in both high-performance and low-power modes. This eliminates the need for separate code images and compilation processes for different processors, reducing code storage requirements while maintaining the ability to optimize power consumption through runtime mode switching.
Solution Approach 2:
The system dynamically switches between operational modes (high-performance and low-power) based on real-time requirements, rather than requiring static separate processors. This dynamic approach allows a single code base to be executed efficiently in different modes without needing separate compiled versions, reducing overall code storage needs.
3Productivity
If a single CPU operates at high voltage and frequency for high performance, then computational power is maximized, but power consumption increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting voltage and frequency levels based on computational requirements. The single CPU can operate at high voltage and frequency for maximum computational power when needed, and switch to lower voltage and frequency for reduced power consumption during less demanding tasks, thus resolving the contradiction between performance and power usage.
Solution Approach 2:
The system implements dynamic operational modes where the CPU automatically adjusts its performance characteristics (voltage, frequency) based on real-time computational demands. This allows the system to maximize computational power when required while minimizing power consumption during idle or low-demand periods, eliminating the need for separate fixed-mode processors.
4Speed
If high speed bus is used for all operations, then performance is maximized, but power consumption increases during low performance operations
Solution Approach 1:
The bus system implements dynamic speed adjustment, operating at high speed when computational performance is required and switching to low-power modes during idle or low-demand periods. This dynamic behavior allows the system to maximize bus performance when needed while minimizing power consumption during low-performance operations, eliminating the need for separate high-speed and low-power bus configurations.
Data Source
AI summary
A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.