Single-Crystal Channel Layer for Memory Devices
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Solution Overview
Problem
The stability of threshold voltages in vertical channel structure memory cells is compromised due to grain boundaries in the channel layer, leading to unstable operation of memory cell strings.
Innovation Solution
A semiconductor pad is formed at the bottom of a channel opening, with a base dopant implanted using ion implantation, and subsequently driven into the channel layer, creating regions with varying doping concentrations to reduce resistance and stabilize threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a deposited semiconductor material (epitaxial poly-silicon) is used for the channel layer, then the manufacturing process is simple, but grain boundaries are easily generated causing threshold voltage variation
Solution Approach 1:
The patent changes the material parameter from deposited poly-silicon to single-crystal semiconductor material, fundamentally altering the crystal structure to eliminate grain boundaries while maintaining manufacturing feasibility through established single-crystal growth techniques
Solution Approach 2:
The patent introduces a composite structure with a doped semiconductor pad at the bottom of the channel opening and a single-crystal channel layer above it, where the doped pad serves as a seed layer that facilitates single-crystal growth and provides electrical contact, creating a multi-layer composite that combines the benefits of doping control with grain boundary-free channel transport
2Ease of manufacture
If grain boundaries are present in the channel layer, then the manufacturing process remains simple, but the current of the channel is greatly reduced and threshold voltage increases
Solution Approach 1:
The patent changes the crystal structure parameter from polycrystalline to single-crystal, eliminating grain boundaries that scatter carriers and reduce mobility, thereby significantly increasing channel current while maintaining manufacturing simplicity through modified deposition or growth processes
Solution Approach 2:
The patent converts the typically harmful grain boundaries into a benefit by using a doped semiconductor pad as a seed layer that promotes single-crystal growth, transforming the manufacturing challenge into an opportunity to achieve superior electrical properties through controlled crystallization
3Manufacturing precision
If grain boundaries are generated in the non-gate-control region, then the threshold voltage of memory cells increases, but the stability of memory cell operation deteriorates
Solution Approach 1:
The patent changes the material parameter from deposited poly-silicon to single-crystal semiconductor material, eliminating grain boundaries in the non-gate-control region that cause threshold voltage variations and operational instability, while maintaining precise threshold voltage control through controlled doping in the single-crystal structure
Solution Approach 2:
The patent converts the harmful effect of grain boundaries causing operational instability into a benefit by using the doped semiconductor pad as a nucleation site for single-crystal growth, ensuring that the channel layer forms without grain boundaries and provides stable, predictable memory cell operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces grain boundary barriers and increases channel current, providing stable threshold voltages for memory cell strings and improving operational stability.
Implementation Method 1
a base dopant implanted into the semiconductor pad by an ion implantation process, and a part of the dopant in the semiconductor pad is driven into the channel layer by heat treatments of the subsequent process
Implementation Method 2
a base dopant implanted into the semiconductor pad by an ion implantation process
Data Source
AI summary
A memory device includes a conductive strip stack structure having conductive strips and insulating layers stacked in a staggered manner and a channel opening passing through the conductive strips and the insulating layer; a memory layer disposed in the channel opening and overlying the conductive strips; a channel layer overlying the memory layer; a semiconductor pad extending upwards from a bottom of the channel opening beyond an upper surface of a bottom conductive strip, in contact with the channel layer, and electrically isolated from the conductive strips; wherein the channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration disposed on the first portion.