Single-Crystal Fin-FET via Laser Epitaxial Growth
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Solution Overview
Problem
The increasing integration density of semiconductor devices leads to short channel effects and undesired on/off characteristics in Fin-FET configurations, necessitating a method to improve gate controllability and current flow while minimizing surface damage during fin formation.
Innovation Solution
A method involving the formation of a single-crystallized seed layer on a semiconductor substrate using laser-induced epitaxial growth, which eliminates the need for etching and allows the gate electrode to contact the seed layer, increasing the channel width and improving electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate electrode line width and channel length are decreased to increase integration density, then the integration density is improved, but short channel effects such as drain induced barrier lowering and punch-through occur
Solution Approach 1:
The patent transitions from planar channel structure to three-dimensional Fin-FET structure by forming vertical fins protruding from the substrate. This dimensional change increases the effective channel width without increasing the planar footprint, thereby improving integration density while maintaining gate controllability through the vertical fin structure that reduces short channel effects
Solution Approach 2:
The channel region is segmented into multiple vertical fins instead of a single planar channel. Each fin acts as an independent current path with its own gate-controlled channel, allowing the gate to effectively control current flow in each segment while collectively achieving high integration density across the device area
2Ease of manufacture
If a non-single crystal seed layer is used and etching is performed to form fins, then the manufacturing process is simplified, but surface damage occurs on the fin structures
Solution Approach 1:
The patent replaces the mechanical etching process with a chemical epitaxial growth process. Instead of removing material through etching to form fins, the method uses selective epitaxial growth to deposit single-crystal semiconductor material in desired fin patterns. This substitution eliminates mechanical surface damage while achieving the same structural outcome
Solution Approach 2:
The patent converts the potential harm of using non-single crystal seed layers (which could lead to poor fin quality) into a benefit by using selective epitaxial growth. The epitaxial process selectively grows high-quality single-crystal fins only in regions where the seed layer is present, transforming the initially problematic non-crystalline seed layer into a beneficial template for forming damage-free single-crystal fin structures
3Productivity
If the channel length is decreased to increase integration density, then the device size is reduced, but the transistor threshold voltage increases due to narrow width effect
Solution Approach 1:
The patent uses vertical fins to increase the effective channel width in the vertical dimension while keeping the planar channel length short. This allows high integration density with short channel lengths while maintaining adequate effective channel width to control threshold voltage and minimize narrow width effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the controllability and current flow of Fin-FETs by forming high-quality, dense-grained single-crystal fins without surface damage, simplifying the process and improving the electrical performance of semiconductor integrated circuit devices.
Implementation Method 1
irradiating the patterned seed layer to single-crystallize the patterned seed layer
Implementation Method 2
irradiating the patterned seed layer to single-crystallize the patterned seed layer
Data Source
AI summary
A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.