Single-Crystal Memory Transistors in Tapered 3D Cavities
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Solution Overview
Problem
As memory devices scale, the area of the substrate required for substrate-based circuitry increases, leading to routing challenges and limitations in supporting a growing quantity of decks and layers, particularly due to the need for circuitry to be located both below and above the stack of memory arrays.
Innovation Solution
The implementation of a memory device with both lower substrate-based circuitry and upper circuitry formed by deposited semiconductor material in a crystalline arrangement, where the semiconductor is deposited into tapered cavities to promote single-grain nucleation, allowing for cohesive single-crystal transistors to be formed above the substrate-based circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If substrate-based circuitry is used to support memory arrays, then circuit functionality is achieved, but substrate area increases leading to routing challenges and limitations in supporting growing quantity of decks
Solution Approach 1:
The patent transitions from planar substrate-based circuitry to vertically stacked three-dimensional circuitry. Memory arrays are arranged in multiple decks stacked above a reduced substrate area, with circuitry distributed across different vertical levels. This dimensional transition allows significantly increased storage capacity without proportional increases in substrate footprint, directly resolving the area constraint while supporting growth in deck quantity.
Solution Approach 2:
The patent implements nested circuitry where upper circuitry is positioned above and integrated with lower circuitry in a vertical stack. The circuitry nests multiple functional layers within a compact vertical volume, allowing complex circuit functionality to be achieved within a small substrate footprint. This nesting approach enables support for growing deck quantities by adding vertical layers rather than expanding horizontal area.
2Adaptability or versatility
If circuitry is located both below and above the stack of memory arrays, then routing flexibility is improved, but substrate area and routing complexity increase
Solution Approach 1:
The patent segments circuitry into distinct lower and upper portions positioned at different vertical levels. Lower circuitry handles specific functions while upper circuitry handles others, with controlled interfaces between levels. This segmentation provides routing flexibility by allowing independent optimization of each segment while reducing overall routing complexity through functional separation and localized interconnections.
Solution Approach 2:
The patent utilizes the vertical dimension to separate circuitry into lower and upper stacks, transforming two-dimensional routing challenges into three-dimensional spatial organization. This vertical separation provides routing flexibility by allowing signals to be routed at different height levels, reducing cross-talk and interference while managing complexity through structured vertical layering rather than planar congestion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the area available for circuitry, alleviates routing challenges, and enables greater scaling of memory devices by supporting a greater quantity of decks within a given footprint, improving memory storage capabilities.
Implementation Method 1
the semiconductor material that is deposited over the one or more decks and that has been heated and cooled to form the semiconductor material in a crystalline arrangement
Implementation Method 2
the semiconductor material may be deposited into tapered cavities that promote nucleation of the crystalline arrangement at a respective single location
Data Source
AI summary
Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.