Single-Crystal Contacts for Semiconductor Memory Devices
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Solution Overview
Problem
Conventional trench transistors in semiconductor memory devices face issues with high resistivity at the tungsten contact junction, increased leakage current due to reduced distance between the gate and source/drain regions, and reduced reliability and yield as devices integrate more tightly and operate at higher speeds.
Innovation Solution
The use of single-crystal conductive contacts formed through selective epitaxial growth (SEG) increases the critical dimension of direct contacts, allowing for a thicker inter-layer dielectric and greater separation between bit and word lines, while also extending the channel length and reducing resistance at the p-n junction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If tungsten contact is used to fill the trench, then the contact can be formed with conventional processes, but the junction between the tungsten contact and the underlying source/drain region creates a relatively narrow p-n junction which is highly resistive
Solution Approach 1:
The patent changes the material parameter from polycrystalline tungsten to single-crystal silicon through selective epitaxial growth. This material substitution fundamentally alters the electrical properties at the contact junction, transforming the highly resistive narrow p-n junction into a low-resistance contact with improved carrier transport properties.
Solution Approach 2:
The patent creates a composite structure where single-crystal silicon forms the contact region with optimized electrical properties, while the underlying substrate and other device regions maintain their conventional materials. This composite approach allows the contact region to have superior electrical characteristics without compromising the overall device fabrication process.
2Productivity
If increased integration is implemented, then the device density and speed are improved, but the distance between the gate and source/drain region is reduced which increases leakage current
Solution Approach 1:
The patent applies local quality by forming single-crystal silicon regions specifically at the contact locations where source/drain regions are exposed. This localized single-crystal formation provides improved electrical properties and better control over leakage current at critical interfaces, while the rest of the device structure can maintain high integration density through conventional scaling.
3Productivity
If increased integration is implemented, then the device density is improved, but photolithographic alignment becomes more critical which reduces yield
Solution Approach 1:
The patent employs preliminary action by using selective epitaxial growth to form single-crystal silicon contacts before final contact hole formation. The epitaxial growth process self-aligns to exposed source/drain regions, creating a buffer zone that provides alignment tolerance for subsequent photolithographic steps. This preliminary structuring reduces the criticality of alignment in high-density integration.
4Reliability
If single-crystal conductive contacts are formed using selective epitaxial growth, then the critical dimension of direct contacts is increased and inter-layer dielectric thickness can be increased, but the fabrication process complexity is increased
Solution Approach 1:
The patent merges multiple functions into the selective epitaxial growth process: it forms the single-crystal contact material, defines the contact geometry, creates alignment buffers, and prepares the surface for subsequent metallization. By combining these functions into a single process step, the overall fabrication complexity is managed while achieving the benefits of increased contact dimension and improved bit line loading capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and integration of semiconductor memory devices by reducing leakage current, improving bit line loading capacitance, and increasing device yield through controlled resistance and extended channel length.
Implementation Method 1
forming a single-crystal conductive contacts using selective epitaxial growth (SEG)
Data Source
AI summary
A memory cell of memory device, comprises an active region of a memory cell defined in a semiconductor substrate, and a conductive gate electrode in a trench of the active region. The gate electrode is isolated from the semiconductor substrate. An insulation layer is on the active region and on the conductive gate electrode. A conductive contact is in the insulation layer on the active region at a side of the gate electrode and isolated from the gate electrode. The contact has a first width at a top portion thereof and a second width at a bottom portion thereof, the first width being greater than the second width. The contact is formed of a single-crystal material.