Single Crystal Oxide Gate Dielectric for Semiconductor Devices

Solution Overview

Problem

The existing methods for forming a crystalline oxide gate dielectric layer in semiconductor devices face challenges such as high crystallization temperatures, incomplete crystallization, and non-ideal properties, especially when deposited over uneven surfaces or after dummy gate removal, limiting material choices and achieving abrupt interfaces with the channel.

Innovation Solution

A single crystal oxide layer is formed early in the manufacturing process over a flat substrate surface before patterning operations, using methods like CVD or ALD at temperatures between 650° C to 1000° C, and then used as a gate dielectric with a metal gate electrode, allowing for precise control and abrupt interfaces with the channel.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If crystalline oxide is deposited over uneven surfaces or after dummy gate removal, then material choices are limited, but manufacturing flexibility and device performance are improved

Engineering Contradiction:

Improvematerial choicesVSAvoidinterface abruptness

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming the crystalline oxide layer early in the manufacturing process, before dummy gate removal and other patterning operations. This early formation ensures the oxide is deposited on a flat substrate surface, guaranteeing abrupt interfaces with the channel while preserving material selection flexibility. The oxide layer is prepared in advance when the surface is most suitable for high-quality deposition.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If high crystallization temperatures are used, then crystalline oxide quality is improved, but process complexity and energy consumption increase

Engineering Contradiction:

Improvecrystalline oxide qualityVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent utilizes parameter changes by depositing the crystalline oxide layer at relatively low temperatures (below typical crystallization temperatures) during early manufacturing stages. The oxide then undergoes in-situ crystallization through subsequent processing steps, effectively changing the temperature parameters dynamically throughout the manufacturing process to achieve high-quality crystalline structures without requiring extremely high processing temperatures at any single stage.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If crystalline oxide is formed early on flat substrate, then abrupt interfaces with channel are achieved, but process timing and scheduling become more critical

Engineering Contradiction:

Improveinterface abruptnessVSAvoidprocess efficiency

Core Design Contradiction:

Manufacturing precisionVSProductivity

Solution Approach 1:

The patent merges multiple functions into the early oxide formation step. The crystalline oxide layer is deposited and then subsequently used as both the gate dielectric and as a reference layer for later alignment operations. This merging of functions eliminates the need for separate reference layer formation steps and simplifies the overall process timing, as the oxide layer serves multiple purposes throughout manufacturing.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of a high-quality single crystal oxide layer with targeted crystallinity, improving gate length scaling and eliminating transition regions, thus enhancing the performance and reliability of semiconductor devices.

Implementation Method 1

A single crystal oxide layer is formed early in the manufacturing process over a flat substrate surface before patterning operations, using methods like CVD or ALD at temperatures between 650° C to 1000° C

Methodology Applied

Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 2

A single crystal oxide layer is formed early in the manufacturing process over a flat substrate surface before patterning operations, using methods like CVD or ALD at temperatures between 650° C to 1000° C

Methodology Applied

Scientific EffectAtomic Layer Deposition:

Implementation Method 3

A single crystal oxide layer is formed early in the manufacturing process over a flat substrate surface before patterning operations, using methods like CVD or ALD at temperatures between 650° C to 1000° C

Methodology Applied

Scientific EffectCrystallization: Crystallisation

Data Source

PatentUS11289580B2Semiconductor device

Publication Date: 2022.03.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

In a method of manufacturing a semiconductor device, a single crystal oxide layer is formed over a substrate. After the single crystal oxide layer is formed, an isolation structure to define an active region is formed. A gate structure is formed over the single crystal oxide layer in the active region. A source/drain structure is formed.