Single Cycle Predictor for Processor Instruction Fetch Latency
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Solution Overview
Problem
The lengthy instruction fetch process in processors is due to the sequential nature of address translation, instruction cache way determination, and data readout steps, which involve significant memory access times and contribute to pipeline latency, especially in high-frequency designs, and misprediction handling is hindered by the length of the instruction fetch pipeline.
Innovation Solution
A branch target buffer (BTB) is used to store set index and way number predictions, allowing parallel access to the instruction cache and translation lookaside buffer, shortening the instruction fetch pipeline and reducing latency by eliminating the need for sequential address translation and cache way determination steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential address translation and cache way determination steps are performed, then memory access is simplified, but instruction fetch latency increases
Solution Approach 1:
The patent pre-calculates and stores the set index and way number in the branch target buffer (BTB) alongside the target address. This preliminary action allows the instruction fetch unit to directly access the correct cache way without performing sequential way determination steps, significantly reducing instruction fetch latency while maintaining a manageable pipeline structure.
Solution Approach 2:
The patent segments the instruction fetch process by pre-computing specific components (set index and way number) separately from the main fetch pipeline. These pre-computed segments are stored in the BTB and retrieved in parallel with address translation, eliminating sequential dependencies and reducing overall fetch latency without excessively complicating the pipeline.
2Loss of time
If parallel access to instruction cache and translation lookaside buffer is implemented, then instruction fetch latency is reduced, but device complexity increases
Solution Approach 1:
The set index and way number are pre-calculated and stored in the BTB during branch instruction processing. This preliminary action enables the instruction fetch unit to immediately access the correct cache way in parallel with address translation, reducing latency without requiring complex dynamic control logic during the fetch process.
Solution Approach 2:
The patent introduces the BTB as an intermediary structure that bridges the branch prediction mechanism and the instruction cache. The BTB stores pre-computed set index and way number information, acting as a mediator that enables parallel access to the instruction cache and translation lookaside buffer without directly coupling their control logic, thus reducing overall system complexity.
3Speed
If long instruction fetch pipeline is used, then high processor clock frequency is achieved, but misprediction penalty increases
Solution Approach 1:
The patent pre-computes the set index and way number and stores them in the BTB before instruction fetch. This preliminary action allows the instruction fetch unit to directly access the correct cache way without traversing a long sequential pipeline for way determination, thereby reducing misprediction penalty while maintaining support for high processor clock frequencies.
Solution Approach 2:
The patent extracts the set index and way number information from the sequential address translation and cache way determination process. By pre-calculating and storing these values in the BTB, the patent removes the need for lengthy sequential way determination steps during instruction fetch, reducing both pipeline latency and misprediction penalty while supporting high clock frequencies.
Data Source
AI summary
A predictor includes a memory having a plurality of entries. Each entry includes a prediction of a hash of a next fetch address produced by a fetch block J of a series of successive fetch blocks in program execution order and a branch direction produced by the fetch block J. An input selects an entry for provision on the output. The output is fed back to the input such that the output provides the prediction of the hash of the next fetch address and the branch direction produced by each fetch block over a series of successive clock cycles. The hash of the next fetch address is insufficient for use by an instruction fetch unit to fetch from an instruction cache a fetch block J+1, whereas the next fetch address itself is sufficient for use by the instruction fetch unit to fetch from the instruction cache the fetch block J+1.