Single Damascene Interconnects via Guide Layer Etching
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Solution Overview
Problem
The dual damascene scheme used in semiconductor manufacturing often results in via profiles and chamfer heights that are difficult to control, leading to 'round' via line ends and blowouts in the dielectric layer, which can cause shorting issues due to uneven etching rates between materials.
Innovation Solution
A method involving a single damascene process with a specific etch stack and guide layers to form interlayer connections, where guide layers are etched to create openings for vias and super vias with substantially vertical sidewalls, and metal fill is deposited to connect conductive lines, ensuring consistent via dimensions and preventing blowouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dual damascene scheme is used to form vias, then interlayer connections can be created, but via profiles and chamfer heights become difficult to control causing round via line ends
Solution Approach 1:
The patent changes the etching parameters by introducing a stop layer at a specific depth, which fundamentally alters the etching process to achieve square via line ends instead of round ends, directly resolving the via profile control issue
2Manufacturing precision
If dual damascene scheme is used to form svias, then interlayer connections can be created, but blowouts occur in the dielectric layer
Solution Approach 1:
The patent applies preliminary anti-action by depositing a stop layer before the etching process, which prevents the etchant from removing the dielectric layer excessively, thereby preventing blowouts before they can occur
Solution Approach 2:
The patent changes the etching depth parameter by introducing a stop layer at a predetermined depth, which controls the etching process to prevent dielectric layer removal beyond the desired depth, eliminating blowouts
3Productivity
If dual damascene scheme is used, then vias can be formed, but dielectric removal rate exceeds other materials causing shortened distance between svias and potential shorting
Solution Approach 1:
The patent applies preliminary anti-action by placing a stop layer that prevents excessive dielectric removal, thereby maintaining adequate spacing between svias and preventing shorting while still allowing efficient via formation
Solution Approach 2:
The patent changes the etching depth parameter through the stop layer mechanism, which controls the removal depth to maintain proper spacing between vias and prevent shorting issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures precise formation of vias and super vias with vertical sidewalls, reducing the risk of shorting by maintaining consistent via dimensions and preventing dielectric layer blowouts, thereby improving the reliability of interlayer connections in semiconductor devices.
Implementation Method 1
etching guide layers following the etch stack to a first capping layer to form a plurality of guide openings, concurrently exposing a first plurality of conductive lines and a second plurality of conductive lines to form a plurality of interlayer connection openings by etching through the plurality of guide openings to remove the first capping layer, an interlayer dielectric, and a second capping layer
Implementation Method 2
depositing a metal fill in the plurality of interlayer connection openings to form the plurality of interlayer connections
Data Source
AI summary
A method is presented for forming interlayer connections in a semiconductor device. The method includes patterning an etch stack to provide for a plurality of interlayer connections, etching guide layers following the etch stack to a first capping layer to form a plurality of guide openings, concurrently exposing a first plurality of conductive lines and a second plurality of conductive lines to form a plurality of interlayer connection openings by etching through the plurality of guide openings to remove the first capping layer, an interlayer dielectric, and a second capping layer, and depositing a metal fill in the plurality of interlayer connection openings to form the plurality of interlayer connections.