Single Delay Line DLL Circuit for Low-Power Clock Delay Selection

The patent merges multiple delay lines into a single shared delay line that is time-multiplexed to serve multiple delay clock outputs. Instead of having separate delay lines for each delay clock, one delay line is reused across different time periods to generate multiple delay clocks, thereby reducing the layout area while maintaining the required clock delay functionality.

The patent introduces dynamic control mechanisms (delay control signals) that enable the single delay line to be selectively activated at different time periods. This dynamic switching allows the delay line to serve multiple functions sequentially, adapting its output to different delay clock requirements without requiring multiple static delay lines.

The patent combines multiple delay line operations into a single shared delay line that is activated only when needed. By consolidating the delay functionality into one resource that is time-shared, the patent eliminates the continuous power consumption that would occur if multiple delay lines were always active, thereby reducing overall power usage while maintaining clock delay functionality.

The patent employs periodic activation of the single delay line through time-multiplexing, where the delay line is enabled only during specific time periods when delay clocks are needed. This periodic operation replaces continuous operation of multiple delay lines, significantly reducing power consumption by keeping the delay line inactive during periods when it is not required.

The patent implements dynamic enable/disable control of the delay line based on actual demand. Instead of continuously enabling delay units, the system uses control signals to activate the delay line only when delay clocks are required, and disables it during idle periods. This dynamic approach maintains clock signal availability when needed while minimizing power consumption during non-critical periods.

The patent ensures continuous availability of delay clocks through time-multiplexed operation, where the single delay line is systematically activated across different time periods to serve all required delay clock outputs. This continuous useful action is achieved not by continuously powering all delay units, but by ensuring that the single delay line is periodically activated to cover all necessary time slots, maintaining reliability while reducing power usage.