Single Delay Line DLL Circuit for Low-Jitter Clock Synchronization
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Solution Overview
Problem
High-frequency clock synchronization in synchronous memory devices faces challenges due to internal circuitry delays, leading to phase shifts and jitter in clock signals, which can result in invalid commands and data transfer issues, especially when using traditional delay-locked loops (DLLs) at high frequencies.
Innovation Solution
A synchronization circuit using a single delay line with even and odd clock lines and a phase mixer to generate intermediate clocks, restricting intrinsic delay and duty cycle distortion, while maintaining a fixed phase difference between the even and odd clock lines, allowing for seamless phase transitions and effective coarse shifting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a dual delay line architecture is used for clock synchronization, then the lock range is increased, but jitter is introduced and intrinsic delay increases
Solution Approach 1:
The patent merges the coarse delay line and fine delay line into a single unified delay line structure. The delay line includes multiple delay units that can be selectively activated to provide both coarse and fine adjustment capabilities without requiring separate dual delay line architectures, thereby eliminating the jitter and intrinsic delay associated with switching between separate delay lines while maintaining extended lock range
Solution Approach 2:
The patent implements dynamic control of delay units through select signals that enable or disable specific delay units based on the synchronization requirements. This dynamic activation/deactivation mechanism allows the single delay line to adaptively provide different delay amounts for coarse and fine tuning, achieving both extended lock range and maintained signal integrity without the need for dual static delay line structures
2Productivity
If the frequency of the external clock signal is increased to increase data transfer rate, then productivity is improved, but phase shift between internal and external clock signals increases
Solution Approach 1:
The patent segments the delay line into multiple discrete delay units that can be independently controlled. Each delay unit provides a specific delay amount, and by selectively activating different combinations of delay units, the circuit can precisely compensate for phase shifts at high frequencies. This segmentation allows for fine-grained timing adjustment that maintains synchronization accuracy even when external clock frequency increases
Solution Approach 2:
The patent changes the delay parameter by dynamically adjusting which delay units are activated based on the external clock frequency and phase requirements. The control circuit modifies the delay amount in the delay line in response to frequency changes, enabling the system to maintain precise timing synchronization across a wide range of operating frequencies without sacrificing productivity
3Adaptability or versatility
If additional delay units are coupled to the delay line to increase lock range, then adaptability is improved, but intrinsic delay and drive to load ratio increase
Solution Approach 1:
The patent employs dynamic control where delay units are selectively activated or deactivated based on the required lock range and operating conditions. Not all delay units are active simultaneously; instead, the control circuit enables only the necessary number of delay units to achieve the desired synchronization, thereby minimizing intrinsic delay while maintaining sufficient lock range for the given application
Data Source
AI summary
Methods, circuits, devices, and systems are provided, including a delay line for a delay-locked loop. One method includes providing a reference clock to a first delay unit in a delay line. The delay line includes a number of delay units coupled together. Even delay units, among the delay units, are coupled to an even clock line to generate a first intermediate clock. Odd delay units are coupled to an odd clock line to generate a second intermediate clock. The even and odd delay units are configured to in a manner intended to restrict an increase in drive to load ratio and to intrinsic delay as additional delay units are coupled to the number of delay units.