Single Device Driver Circuit for 3D Memory Array Leakage Control

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Solution Overview

Problem

Existing memory array designs with small pitch dimensions face challenges in efficiently draining charge from bit lines and controlling bias voltages, leading to increased complexity and leakage currents, particularly in three-dimensional memory arrays.

Innovation Solution

The implementation of a single device array line driver and decoder-controlled bleeder diode array that synchronizes the control of unselected and selected bias voltage paths using bleeder diodes, reducing physical size and complexity by eliminating the need for a separate drainage controller and using bleeder diodes to manage unselected bit and word line voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate drainage controller is used to drain charge from bit lines, then charge drainage is achieved, but device complexity increases

Engineering Contradiction:
Improvecharge drainageVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the drainage controller functionality with the word line driver circuit by sharing the control logic and using the same driver structure to control both the word line and the drainage operation. This integration eliminates the need for a completely separate drainage controller, reducing overall device complexity while maintaining effective charge drainage capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The word line driver is designed to perform multiple functions: driving the word line during normal memory operations and controlling the drainage of charge from bit lines during erase operations. This multi-functional design reduces the need for dedicated separate circuits, thereby reducing device complexity while maintaining reliable charge drainage.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If multiple control circuits are used for bias voltage control, then voltage control precision is improved, but device complexity increases

Engineering Contradiction:
Improvevoltage control precisionVSAvoidcontrol circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the bias voltage control functionality into the existing driver circuits. The driver circuits are designed to provide precise voltage control for both word lines and bit lines while integrating the control logic, thereby maintaining voltage control precision without requiring separate dedicated control circuits for each function.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The control circuits are designed to dynamically adjust their operation based on the current mode (read, write, erase). The same control logic adapts its behavior to provide appropriate voltage levels and drainage control for different operations, maintaining precision while reducing the need for multiple static control circuits.

Inventive Principle:
Principle #15Dynamics

3Loss of energy

If bleeder diodes are used to control unselected line voltages, then leakage currents are reduced, but manufacturing complexity increases

Engineering Contradiction:
Improveleakage currentVSAvoidfabrication complexity
Core Design Contradiction:
Loss of energyVSEase of manufacture

Solution Approach 1:

The bleeder diodes are integrated into the memory cell structure itself, using the same diode formation process for both memory cells and bleeder diodes. This homogeneous approach uses identical fabrication steps to create both functional elements, thereby reducing manufacturing complexity while effectively controlling leakage currents through the bleeder diodes.

Inventive Principle:
Principle #33Homogeneity

Data Source

PatentEP2606488B1Single device driver circuit to control three-dimensional memory element array
Publication Date: 2016.12.21 SANDISK TECHNOLOGIES LLC
  • EP2606488B1 patent drawing
  • EP2606488B1 patent drawing
  • EP2606488B1 patent drawing

AI summary

A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers (163) with gates coupled to a bit line decoder (120) control lead (322), sources/drains coupled to a bit line driver (304), and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode (300) coupled between a bit line and a first bleeder diode controller (314), and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller (314) connects the first bleeder diode (300) to low voltage (305) in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal.